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Searched refs:CP0SRSC2_SRS9 (Results 1 – 22 of 22) sorted by relevance

/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-mips/
H A Dtranslate_init.c387 (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
H A Dcpu.h309 #define CP0SRSC2_SRS9 20
/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-mips/
H A Dtranslate_init.c387 (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
H A Dcpu.h309 #define CP0SRSC2_SRS9 20 macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/mips/
H A Dcpu.h308 #define CP0SRSC2_SRS9 20 macro
H A Dtranslate_init.inc.c287 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
/dports/emulators/qemu-utils/qemu-4.2.1/target/mips/
H A Dcpu.h713 #define CP0SRSC2_SRS9 20 macro
H A Dtranslate_init.inc.c287 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
/dports/emulators/qemu5/qemu-5.2.0/target/mips/
H A Dcpu.h715 #define CP0SRSC2_SRS9 20 macro
H A Dtranslate_init.c.inc287 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/mips/
H A Dcpu.h713 #define CP0SRSC2_SRS9 20 macro
H A Dtranslate_init.inc.c287 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
/dports/emulators/qemu42/qemu-4.2.1/target/mips/
H A Dcpu.h713 #define CP0SRSC2_SRS9 20 macro
H A Dtranslate_init.inc.c287 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/mips/
H A Dcpu.h719 #define CP0SRSC2_SRS9 20
H A Dcpu-defs.c.inc287 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
/dports/emulators/qemu/qemu-6.2.0/target/mips/
H A Dcpu.h719 #define CP0SRSC2_SRS9 20 macro
H A Dcpu-defs.c.inc287 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
/dports/emulators/qemu60/qemu-6.0.0/target/mips/
H A Dcpu.h719 #define CP0SRSC2_SRS9 20 macro
H A Dcpu-defs.c.inc287 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/mips/
H A Dcpu.h806 #define CP0SRSC2_SRS9 20 macro
H A Dtranslate_init.inc.c287 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |