| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/clk/renesas/ |
| H A D | clk-r8a73a4.c | 28 #define CPG_PLL0CR 0xd8 macro
96 u32 value = readl(cpg->reg + CPG_PLL0CR); in r8a73a4_cpg_register_clock()
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| H A D | clk-sh73a0.c | 30 #define CPG_PLL0CR 0xd8 macro
97 enable_reg += CPG_PLL0CR; in sh73a0_cpg_register_clock()
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/clk/renesas/ |
| H A D | clk-r8a73a4.c | 28 #define CPG_PLL0CR 0xd8 macro
96 u32 value = readl(cpg->reg + CPG_PLL0CR); in r8a73a4_cpg_register_clock()
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| H A D | clk-sh73a0.c | 30 #define CPG_PLL0CR 0xd8 macro
97 enable_reg += CPG_PLL0CR; in sh73a0_cpg_register_clock()
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/clk/renesas/ |
| H A D | clk-sh73a0.c | 30 #define CPG_PLL0CR 0xd8 macro
97 enable_reg += CPG_PLL0CR; in sh73a0_cpg_register_clock()
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| H A D | clk-r8a73a4.c | 28 #define CPG_PLL0CR 0xd8 macro
96 u32 value = readl(cpg->reg + CPG_PLL0CR); in r8a73a4_cpg_register_clock()
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| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/clk/renesas/ |
| H A D | clk-rcar-gen2.c | 26 #define CPG_PLL0CR 0x00d8 macro
149 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
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| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/clk/renesas/ |
| H A D | clk-rcar-gen2.c | 26 #define CPG_PLL0CR 0x00d8 macro
149 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/clk/renesas/ |
| H A D | clk-rcar-gen2.c | 26 #define CPG_PLL0CR 0x00d8 macro
149 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/clk/renesas/ |
| H A D | clk-rcar-gen2.c | 26 #define CPG_PLL0CR 0x00d8 macro
149 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
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| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/drivers/clk/renesas/ |
| H A D | clk-rcar-gen2.c | 26 #define CPG_PLL0CR 0x00d8 macro
149 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
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| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/renesas/ |
| H A D | clk-rcar-gen2.c | 26 #define CPG_PLL0CR 0x00d8 macro
153 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
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| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/renesas/ |
| H A D | clk-rcar-gen2.c | 26 #define CPG_PLL0CR 0x00d8 macro
153 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
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| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/renesas/ |
| H A D | clk-rcar-gen2.c | 26 #define CPG_PLL0CR 0x00d8 macro
153 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
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| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/renesas/ |
| H A D | clk-rcar-gen2.c | 26 #define CPG_PLL0CR 0x00d8 macro
153 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
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| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/renesas/ |
| H A D | clk-rcar-gen2.c | 26 #define CPG_PLL0CR 0x00d8 macro
153 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
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| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/renesas/ |
| H A D | clk-rcar-gen2.c | 26 #define CPG_PLL0CR 0x00d8 macro
153 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
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| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/clk/renesas/ |
| H A D | clk-rcar-gen2.c | 26 #define CPG_PLL0CR 0x00d8 macro
153 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
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| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/renesas/ |
| H A D | clk-rcar-gen2.c | 26 #define CPG_PLL0CR 0x00d8 macro
153 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
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| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/renesas/ |
| H A D | clk-rcar-gen2.c | 26 #define CPG_PLL0CR 0x00d8 macro
153 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
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| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/renesas/ |
| H A D | clk-rcar-gen2.c | 26 #define CPG_PLL0CR 0x00d8 macro
153 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
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| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/renesas/ |
| H A D | clk-rcar-gen2.c | 26 #define CPG_PLL0CR 0x00d8 macro
153 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
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| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/renesas/ |
| H A D | clk-rcar-gen2.c | 26 #define CPG_PLL0CR 0x00d8 macro
153 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
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| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/renesas/ |
| H A D | clk-rcar-gen2.c | 26 #define CPG_PLL0CR 0x00d8 macro
153 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
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| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/renesas/ |
| H A D | clk-rcar-gen2.c | 26 #define CPG_PLL0CR 0x00d8 macro
153 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
|