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Searched refs:CPLD_READ (Results 1 – 25 of 1443) sorted by relevance

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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-sopine/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-chip/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/board/freescale/t104xrdb/
H A Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
72 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); in cpld_dump_regs()
[all …]

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