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Searched refs:CPU_MIPS32R2 (Results 1 – 25 of 83) sorted by relevance

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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/mips/
H A Dmips-defs.h71 #define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS_R2) macro
72 #define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2)
75 #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS_R3)
H A Dcpu-defs.c.inc158 .insn_flags = CPU_MIPS32R2,
179 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
201 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
223 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
249 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
297 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
323 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2,
343 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
364 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
/dports/emulators/qemu/qemu-6.2.0/target/mips/
H A Dmips-defs.h71 #define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS_R2) macro
72 #define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2)
75 #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS_R3)
H A Dcpu-defs.c.inc158 .insn_flags = CPU_MIPS32R2,
179 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
201 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
223 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
249 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
297 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
323 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2,
343 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
364 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
/dports/emulators/qemu60/qemu-6.0.0/target/mips/
H A Dmips-defs.h71 #define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS_R2) macro
72 #define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2)
75 #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS_R3)
H A Dcpu-defs.c.inc158 .insn_flags = CPU_MIPS32R2,
179 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
201 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
223 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
249 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
297 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
323 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2,
343 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
364 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-mips/
H A Dmips-defs.h71 #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) macro
72 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
75 #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
H A Dtranslate_init.c256 CPU_MIPS32R2,
286 CPU_MIPS32R2 | ASE_MIPS16,
316 CPU_MIPS32R2 | ASE_MIPS16,
348 CPU_MIPS32R2 | ASE_MIPS16,
396 CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
428 CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
/dports/emulators/qemu-utils/qemu-4.2.1/target/mips/
H A Dmips-defs.h79 #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) macro
80 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
83 #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
H A Dtranslate_init.inc.c158 .insn_flags = CPU_MIPS32R2,
179 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
201 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
223 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
249 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
297 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
323 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2,
343 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
364 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-mips/
H A Dmips-defs.h71 #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) macro
72 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
75 #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
H A Dtranslate_init.c256 CPU_MIPS32R2,
286 CPU_MIPS32R2 | ASE_MIPS16,
316 CPU_MIPS32R2 | ASE_MIPS16,
348 CPU_MIPS32R2 | ASE_MIPS16,
396 CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
428 CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/mips/
H A Dmips-defs.h79 #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) macro
80 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
83 #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
H A Dtranslate_init.inc.c158 .insn_flags = CPU_MIPS32R2,
179 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
201 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
223 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
249 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
297 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
323 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2,
343 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
364 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/mips/
H A Dmips-defs.h76 #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) macro
77 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
80 #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
H A Dtranslate_init.inc.c158 .insn_flags = CPU_MIPS32R2,
179 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
201 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
223 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
249 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
297 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
323 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
343 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
364 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
/dports/emulators/qemu42/qemu-4.2.1/target/mips/
H A Dmips-defs.h79 #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) macro
80 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
83 #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
H A Dtranslate_init.inc.c158 .insn_flags = CPU_MIPS32R2,
179 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
201 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
223 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
249 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
297 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
323 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2,
343 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
364 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/mips/
H A Dmips-defs.h79 #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) macro
80 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
83 #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
H A Dtranslate_init.inc.c158 .insn_flags = CPU_MIPS32R2,
179 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
201 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
223 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
249 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
297 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
323 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2,
343 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
364 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
/dports/emulators/qemu5/qemu-5.2.0/target/mips/
H A Dmips-defs.h86 #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) macro
87 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
90 #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
H A Dtranslate_init.c.inc158 .insn_flags = CPU_MIPS32R2,
179 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
201 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
223 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
249 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
297 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
323 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2,
343 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
364 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
/dports/lang/gnatdroid-binutils-x86/binutils-2.27/gas/config/
H A Dtc-mips.c18775 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18776 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18777 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18779 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18780 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18784 ISA_MIPS32R2, CPU_MIPS32R2 },
18786 ISA_MIPS32R2, CPU_MIPS32R2 },
18787 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18788 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18789 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
[all …]
/dports/devel/gnulibiberty/binutils-2.37/gas/config/
H A Dtc-mips.c20063 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20064 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20065 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20067 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20068 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20072 ISA_MIPS32R2, CPU_MIPS32R2 },
20074 ISA_MIPS32R2, CPU_MIPS32R2 },
20075 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20076 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20077 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
[all …]
/dports/devel/arm-elf-binutils/binutils-2.37/gas/config/
H A Dtc-mips.c20063 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20064 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20065 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20067 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20068 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20072 ISA_MIPS32R2, CPU_MIPS32R2 },
20074 ISA_MIPS32R2, CPU_MIPS32R2 },
20075 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20076 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20077 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
[all …]

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