| /dports/emulators/dynamips-community/dynamips-0.2.17/stable/ |
| H A D | cpu.c | 151 CPU_MIPS64(cpu)->vm = vm; in cpu_create()
152 CPU_MIPS64(cpu)->gen = cpu; in cpu_create()
153 mips64_init(CPU_MIPS64(cpu)); in cpu_create()
160 mips64_jit_init(CPU_MIPS64(cpu)); in cpu_create()
204 mips64_delete(CPU_MIPS64(cpu)); in cpu_delete()
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| H A D | cpu.h | 133 #define CPU_MIPS64(cpu) (&(cpu)->sp.mips64_cpu) macro
141 return(CPU_MIPS64(cpu)->pc); in cpu_get_pc()
154 return(CPU_MIPS64(cpu)->perf_counter); in cpu_get_perf_counter()
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| H A D | mips64.c | 142 CPU_MIPS64(cpu)->idle_pc = addr; in mips64_set_idle_pc()
201 cpu_mips_t *mcpu = CPU_MIPS64(cpu); in mips64_get_idling_pc()
301 boot_cpu = CPU_MIPS64(vm->boot_cpu); in mips64_vm_set_irq()
319 boot_cpu = CPU_MIPS64(vm->boot_cpu); in mips64_vm_clear_irq()
545 cpu_mips_t *mcpu = CPU_MIPS64(cpu); in mips64_add_breakpoint()
563 cpu_mips_t *mcpu = CPU_MIPS64(cpu); in mips64_remove_breakpoint()
593 CPU_MIPS64(cpu)->gpr[reg] = val; in mips64_reg_set()
599 cpu_mips_t *mcpu = CPU_MIPS64(cpu); in mips64_dump_regs()
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| /dports/emulators/dynamips-community/dynamips-0.2.17/unstable/ |
| H A D | cpu.c | 153 CPU_MIPS64(cpu)->vm = vm; in cpu_create()
154 CPU_MIPS64(cpu)->gen = cpu; in cpu_create()
155 mips64_init(CPU_MIPS64(cpu)); in cpu_create()
162 mips64_jit_init(CPU_MIPS64(cpu)); in cpu_create()
206 mips64_delete(CPU_MIPS64(cpu)); in cpu_delete()
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| H A D | cpu.h | 146 #define CPU_MIPS64(cpu) (&(cpu)->sp.mips64_cpu) macro
154 return(CPU_MIPS64(cpu)->pc); in cpu_get_pc()
167 return(CPU_MIPS64(cpu)->perf_counter); in cpu_get_perf_counter()
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| H A D | mips64.c | 144 CPU_MIPS64(cpu)->idle_pc = addr; in mips64_set_idle_pc()
203 cpu_mips_t *mcpu = CPU_MIPS64(cpu); in mips64_get_idling_pc()
303 boot_cpu = CPU_MIPS64(vm->boot_cpu); in mips64_vm_set_irq()
321 boot_cpu = CPU_MIPS64(vm->boot_cpu); in mips64_vm_clear_irq()
630 cpu_mips_t *mcpu = CPU_MIPS64(cpu); in mips64_add_breakpoint()
648 cpu_mips_t *mcpu = CPU_MIPS64(cpu); in mips64_remove_breakpoint()
678 CPU_MIPS64(cpu)->gpr[reg] = val; in mips64_reg_set()
684 cpu_mips_t *mcpu = CPU_MIPS64(cpu); in mips64_dump_regs()
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| /dports/emulators/unicorn/unicorn-1.0.2/qemu/target-mips/ |
| H A D | mips-defs.h | 68 #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) macro
72 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
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| /dports/emulators/qemu-utils/qemu-4.2.1/target/mips/ |
| H A D | mips-defs.h | 76 #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) macro
80 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
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| /dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-mips/ |
| H A D | mips-defs.h | 68 #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) macro
72 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
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| H A D | translate_init.c | 555 CPU_MIPS64,
588 CPU_MIPS64,
623 CPU_MIPS64 | ASE_MIPS3D,
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/target/mips/ |
| H A D | mips-defs.h | 76 #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) macro
80 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
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| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/mips/ |
| H A D | mips-defs.h | 73 #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) macro
77 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
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| /dports/emulators/qemu42/qemu-4.2.1/target/mips/ |
| H A D | mips-defs.h | 76 #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) macro
80 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
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| /dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/mips/ |
| H A D | mips-defs.h | 76 #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) macro
80 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
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| /dports/emulators/qemu5/qemu-5.2.0/target/mips/ |
| H A D | mips-defs.h | 83 #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) macro
87 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
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| /dports/emulators/dynamips-community/dynamips-0.2.17/common/ |
| H A D | dev_c3600.c | 411 mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R4700); in c3620_init()
433 mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R4700); in c3640_init()
468 mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R527x); in c3660_init()
584 cpu = CPU_MIPS64(gen); in c3600_init_platform()
691 cpu = CPU_MIPS64(vm->boot_cpu); in c3600_boot_ios()
726 cpu_mips_t *cpu0 = CPU_MIPS64(vm->boot_cpu); in c3600_set_irq()
748 cpu_mips_t *cpu0 = CPU_MIPS64(vm->boot_cpu); in c3600_clear_irq()
792 cpu0 = CPU_MIPS64(vm->boot_cpu); in c3600_init_instance()
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| H A D | dev_c2691.c | 311 mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R7000); in c2691_init()
410 cpu = CPU_MIPS64(gen); in c2691_init_platform()
509 cpu = CPU_MIPS64(vm->boot_cpu); in c2691_boot_ios()
544 cpu_mips_t *cpu0 = CPU_MIPS64(vm->boot_cpu); in c2691_set_irq()
566 cpu_mips_t *cpu0 = CPU_MIPS64(vm->boot_cpu); in c2691_clear_irq()
610 cpu0 = CPU_MIPS64(vm->boot_cpu); in c2691_init_instance()
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| H A D | dev_c3725.c | 325 mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R7000); in c3725_init()
427 cpu = CPU_MIPS64(gen); in c3725_init_platform()
526 cpu = CPU_MIPS64(vm->boot_cpu); in c3725_boot_ios()
561 cpu_mips_t *cpu0 = CPU_MIPS64(vm->boot_cpu); in c3725_set_irq()
583 cpu_mips_t *cpu0 = CPU_MIPS64(vm->boot_cpu); in c3725_clear_irq()
627 cpu0 = CPU_MIPS64(vm->boot_cpu); in c3725_init_instance()
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| H A D | dev_c6msfc1.c | 340 mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R5000); in c6msfc1_init_hw()
474 cpu0 = CPU_MIPS64(gen0); in c6msfc1_init_platform()
584 cpu = CPU_MIPS64(vm->boot_cpu); in c6msfc1_boot_ios()
619 cpu_mips_t *cpu0 = CPU_MIPS64(vm->boot_cpu); in c6msfc1_set_irq()
641 cpu_mips_t *cpu0 = CPU_MIPS64(vm->boot_cpu); in c6msfc1_clear_irq()
680 cpu0 = CPU_MIPS64(vm->boot_cpu); in c6msfc1_init_instance()
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| H A D | dev_c3745.c | 351 mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R7000); in c3745_init()
462 cpu = CPU_MIPS64(gen); in c3745_init_platform()
561 cpu = CPU_MIPS64(vm->boot_cpu); in c3745_boot_ios()
596 cpu_mips_t *cpu0 = CPU_MIPS64(vm->boot_cpu); in c3745_set_irq()
618 cpu_mips_t *cpu0 = CPU_MIPS64(vm->boot_cpu); in c3745_clear_irq()
662 cpu0 = CPU_MIPS64(vm->boot_cpu); in c3745_init_instance()
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| H A D | dev_c6sup1.c | 408 mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R5000); in c6sup1_init_hw()
540 cpu0 = CPU_MIPS64(gen0); in c6sup1_init_platform()
650 cpu = CPU_MIPS64(vm->boot_cpu); in c6sup1_boot_ios()
685 cpu_mips_t *cpu0 = CPU_MIPS64(vm->boot_cpu); in c6sup1_set_irq()
707 cpu_mips_t *cpu0 = CPU_MIPS64(vm->boot_cpu); in c6sup1_clear_irq()
746 cpu0 = CPU_MIPS64(vm->boot_cpu); in c6sup1_init_instance()
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| H A D | dev_c7200.c | 891 mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R4600); in c7200_init_npe100()
939 mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R4700); in c7200_init_npe150()
995 mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R527x); in c7200_init_npe175()
1040 mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R5000); in c7200_init_npe200()
1096 mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R527x); in c7200_init_npe225()
1140 mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R7000); in c7200_init_npe300()
1481 cpu0 = CPU_MIPS64(gen0); in c7200m_init_platform()
1718 cpu = CPU_MIPS64(vm->boot_cpu); in c7200m_boot_ios()
1803 cpu_mips_t *cpu0 = CPU_MIPS64(vm->boot_cpu); in c7200m_set_irq()
1825 cpu_mips_t *cpu0 = CPU_MIPS64(vm->boot_cpu); in c7200m_clear_irq()
[all …]
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| /dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/mips/ |
| H A D | mips-defs.h | 64 #define CPU_MIPS64 (ISA_MIPS3) macro
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| /dports/emulators/qemu/qemu-6.2.0/target/mips/ |
| H A D | mips-defs.h | 64 #define CPU_MIPS64 (ISA_MIPS3) macro
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| /dports/emulators/qemu60/qemu-6.0.0/target/mips/ |
| H A D | mips-defs.h | 64 #define CPU_MIPS64 (ISA_MIPS3) macro
|