/dports/emulators/qemu5/qemu-5.2.0/target/mips/ |
H A D | mips-defs.h | 87 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) macro 91 #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3) 104 #define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT)
|
H A D | translate_init.c.inc | 637 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, 658 .insn_flags = CPU_MIPS64R2, 682 .insn_flags = CPU_MIPS64R2, 917 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
|
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/mips/ |
H A D | mips-defs.h | 72 #define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2) macro 76 #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3)
|
H A D | cpu-defs.c.inc | 639 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, 660 .insn_flags = CPU_MIPS64R2, 684 .insn_flags = CPU_MIPS64R2, 833 .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A | 891 .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A | 921 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
|
/dports/emulators/qemu/qemu-6.2.0/target/mips/ |
H A D | mips-defs.h | 72 #define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2) macro 76 #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3)
|
H A D | cpu-defs.c.inc | 638 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, 659 .insn_flags = CPU_MIPS64R2, 683 .insn_flags = CPU_MIPS64R2, 832 .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A | 891 .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A | 921 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
|
/dports/emulators/qemu60/qemu-6.0.0/target/mips/ |
H A D | mips-defs.h | 72 #define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2) macro 76 #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3)
|
H A D | cpu-defs.c.inc | 639 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, 660 .insn_flags = CPU_MIPS64R2, 684 .insn_flags = CPU_MIPS64R2, 833 .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A | 891 .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A | 921 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
|
/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-mips/ |
H A D | mips-defs.h | 72 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) macro 76 #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
|
H A D | translate_init.c | 660 CPU_MIPS64R2 | ASE_MIPS3D, 801 CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
|
/dports/emulators/qemu-utils/qemu-4.2.1/target/mips/ |
H A D | mips-defs.h | 80 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) macro 84 #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
|
H A D | translate_init.inc.c | 636 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, 657 .insn_flags = CPU_MIPS64R2, 681 .insn_flags = CPU_MIPS64R2, 830 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
|
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-mips/ |
H A D | mips-defs.h | 72 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) macro 76 #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
|
H A D | translate_init.c | 660 CPU_MIPS64R2 | ASE_MIPS3D, 801 CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
|
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/mips/ |
H A D | mips-defs.h | 80 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) macro 84 #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
|
H A D | translate_init.inc.c | 636 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, 657 .insn_flags = CPU_MIPS64R2, 681 .insn_flags = CPU_MIPS64R2, 830 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
|
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/mips/ |
H A D | mips-defs.h | 77 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) macro 81 #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
|
H A D | translate_init.inc.c | 635 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, 656 .insn_flags = CPU_MIPS64R2, 680 .insn_flags = CPU_MIPS64R2, 789 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
|
/dports/emulators/qemu42/qemu-4.2.1/target/mips/ |
H A D | mips-defs.h | 80 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) macro 84 #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
|
H A D | translate_init.inc.c | 636 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, 657 .insn_flags = CPU_MIPS64R2, 681 .insn_flags = CPU_MIPS64R2, 830 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
|
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/mips/ |
H A D | mips-defs.h | 80 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) macro 84 #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
|
H A D | translate_init.inc.c | 653 .insn_flags = CPU_MIPS64R2, 695 .insn_flags = CPU_MIPS64R2, 753 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, 774 .insn_flags = CPU_MIPS64R2, 798 .insn_flags = CPU_MIPS64R2, 947 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
|
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/include/opcode/ |
H A D | mips.h | 480 #define CPU_MIPS64R2 65
|
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/include/opcode/ |
H A D | mips.h | 490 #define CPU_MIPS64R2 65 macro
|
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/include/opcode/ |
H A D | mips.h | 480 #define CPU_MIPS64R2 65 macro
|