Searched refs:CSIII_REG_IPL_EMU (Results 1 – 1 of 1) sorted by relevance
58 #define CSIII_REG_IPL_EMU 0x06 // 0x30 macro197 bool active = (io_reg[CSIII_REG_IPL_EMU] & P5_DISABLE_INT) == 0; in check_ppc_int_lvl()201 uae_u8 ppcipl = (~io_reg[CSIII_REG_IPL_EMU]) & P5_PPC_IPL_MASK; in check_ppc_int_lvl()220 bool active = (io_reg[CSIII_REG_IPL_EMU] & P5_DISABLE_INT) == 0; in ppc_interrupt()228 uae_u8 ppcipl = (~io_reg[CSIII_REG_IPL_EMU]) & P5_PPC_IPL_MASK; in ppc_interrupt()231 io_reg[CSIII_REG_IPL_EMU] &= ~P5_M68k_IPL_MASK; in ppc_interrupt()232 io_reg[CSIII_REG_IPL_EMU] |= (new_m68k_ipl << 3) ^ P5_M68k_IPL_MASK; in ppc_interrupt()993 } else if (reg == CSIII_REG_IPL_EMU) { in blizzardio_bget()1228 } else if (addr == CSIII_REG_IPL_EMU) { in blizzardio_bput()1456 io_reg[CSIII_REG_IPL_EMU] = 0x40; in cpuboard_reset()