Searched refs:CSR0_INTR (Results 1 – 15 of 15) sorted by relevance
131 if (m_csr[0] & CSR0_INTR) in update_interrupts()301 m_csr[0] |= CSR0_RINT | CSR0_INTR; in recv_complete_cb()521 m_csr[0] |= CSR0_TINT | CSR0_INTR; in send_complete_cb()651 m_csr[0] |= CSR0_INTR; in regs_w()653 m_csr[0] &= ~CSR0_INTR; in regs_w()
66 CSR0_INTR = 0x0080, // interrupt flag enumerator
27 #define CSR0_INTR 0x0080 /* Interrupt Flag (R) */ macro
219 #define CSR0_INTR 0x0080 /* interrupt active (R) */ macro
319 #define CSR0_INTR 0x0080 /* interrupt active (R) */ macro
68 #define CSR0_INTR 0x0080 macro549 csr[0] &= ~CSR0_INTR; in rethink_a2065()551 csr[0] |= CSR0_INTR; in rethink_a2065()552 if ((csr[0] & (CSR0_INTR | CSR0_INEA)) == (CSR0_INTR | CSR0_INEA)) in rethink_a2065()
77 #define CSR0_INTR 0x0080 macro572 csr[0] &= ~CSR0_INTR; in rethink_a2065()574 csr[0] |= CSR0_INTR; in rethink_a2065()575 if ((csr[0] & (CSR0_INTR | CSR0_INEA)) == (CSR0_INTR | CSR0_INEA)) { in rethink_a2065()