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Searched refs:CSR_WRITE_1 (Results 1 – 20 of 20) sorted by relevance

/dports/misc/rump/buildrump.sh-b914579/src/sys/dev/ic/
H A Dcom.c132 #define CSR_WRITE_1(r, o, v) \ macro
143 #define CSR_WRITE_1(r, o, v) \ macro
349 CSR_WRITE_1(regs, COM_REG_IIR, 0); in com_probe_subr()
475 CSR_WRITE_1(regsp, COM_REG_FIFO, in com_attach_subr()
483 CSR_WRITE_1(regsp, COM_REG_FIFO, in com_attach_subr()
487 CSR_WRITE_1(regsp, COM_REG_FIFO, in com_attach_subr()
510 CSR_WRITE_1(regsp, COM_REG_EFR, 0); in com_attach_subr()
581 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); in com_attach_subr()
2058 CSR_WRITE_1(regsp, COM_REG_HALT, in comintr()
2398 CSR_WRITE_1(regsp, COM_REG_FIFO, in cominit()
[all …]
H A Drtl81x9.c147 CSR_WRITE_1(sc, RTK_EECMD, \
151 CSR_WRITE_1(sc, RTK_EECMD, \
195 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM); in rtk_read_eeprom()
218 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); in rtk_read_eeprom()
230 CSR_WRITE_1(sc, RTK_MII, \
234 CSR_WRITE_1(sc, RTK_MII, \
594 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); in rtk_reset()
1343 CSR_WRITE_1(sc, RTK_IDR0 + i, CLLADDR(ifp->if_sadl)[i]); in rtk_init()
1359 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); in rtk_init()
1405 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); in rtk_init()
[all …]
H A Drtl8169.c377 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); in re_reset()
393 CSR_WRITE_1(sc, RTK_LDPS, 1); in re_reset()
700 CSR_WRITE_1(sc, RTK_PMCH, CSR_READ_1(sc, RTK_PMCH) | 0x80); in re_attach()
1433 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); in re_txeof()
1746 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START); in re_start()
1748 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); in re_start()
1828 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); in re_init()
1835 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); in re_init()
1877 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16); in re_init()
1944 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD); in re_init()
[all …]
H A Dwivar.h235 #define CSR_WRITE_1(sc, reg, val) \ macro
257 #define CSR_WRITE_1(sc, reg, val) \ macro
H A Drtl81x9var.h278 #define CSR_WRITE_1(sc, reg, val) \ macro
H A Di82557var.h358 #define CSR_WRITE_1(sc, reg, val) \ macro
H A Di82557.c247 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); in fxp_scb_cmd()
1087 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); in fxp_intr()
1098 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); in fxp_intr()
2012 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI); in fxp_init()
/dports/misc/rump/buildrump.sh-b914579/src/sys/dev/pci/
H A Dif_vge.c263 #define CSR_WRITE_1(sc, reg, val) \ macro
436 CSR_WRITE_1(sc, VGE_EEADDR, addr); in vge_read_eeprom()
467 CSR_WRITE_1(sc, VGE_MIICMD, 0); in vge_miipoll_stop()
488 CSR_WRITE_1(sc, VGE_MIICMD, 0); in vge_miipoll_start()
537 CSR_WRITE_1(sc, VGE_MIIADDR, reg); in vge_miibus_readreg()
574 CSR_WRITE_1(sc, VGE_MIIADDR, reg); in vge_miibus_writereg()
612 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); in vge_cam_clear()
620 CSR_WRITE_1(sc, VGE_CAMADDR, 0); in vge_cam_clear()
677 CSR_WRITE_1(sc, VGE_CAMADDR, 0); in vge_cam_set()
1884 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); in vge_init()
[all …]
H A Dif_ipwreg.h322 #define CSR_WRITE_1(sc, reg, val) \ macro
340 CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \
H A Dif_vr.c283 #define CSR_WRITE_1(sc, reg, val) \ macro
322 CSR_WRITE_1(sc, reg, \
326 CSR_WRITE_1(sc, reg, \
376 CSR_WRITE_1(sc, VR_MIICMD, (val & 0xff) | VR_MIICMD_DIRECTPGM); in vr_mii_bitbang_write()
387 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); in vr_mii_readreg()
399 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); in vr_mii_writereg()
472 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); in vr_setmulti()
508 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); in vr_setmulti()
H A Dif_msk.c219 CSR_WRITE_1(sc, reg, x); in sk_win_write_1()
789 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); in msk_reset()
790 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); in msk_reset()
793 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); in msk_reset()
795 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); in msk_reset()
848 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); in msk_reset()
855 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); in msk_reset()
856 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); in msk_reset()
862 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); in msk_reset()
863 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); in msk_reset()
H A Dif_iwireg.h546 #define CSR_WRITE_1(sc, reg, val) \ macro
564 CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \
H A Dif_alereg.h955 #define CSR_WRITE_1(_sc, reg, val) \ macro
H A Dif_ale.c1396 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, in ale_rx_update_page()
1664 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); in ale_init()
1665 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); in ale_init()
H A Dif_alcreg.h1494 #define CSR_WRITE_1(_sc, reg, val) \ macro
H A Dif_skreg.h1568 #define CSR_WRITE_1(sc, reg, val) \ macro
H A Dif_sk.c306 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); in sk_win_write_1()
308 CSR_WRITE_1(sc, reg, x); in sk_win_write_1()
H A Dif_ipw.c2252 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); in ipw_write_mem_1()
/dports/misc/rump/buildrump.sh-b914579/src/sys/dev/sdmmc/
H A Dsbt.c40 #define CSR_WRITE_1(sc, reg, val) sdmmc_io_write_1((sc)->sc_sf, (reg), (val)) macro
192 CSR_WRITE_1(sc, SBT_REG_IENA, ISTAT_INTRD); in sbt_attach()
304 CSR_WRITE_1(sc, SBT_REG_RPC, 0); in sbt_read_packet()
308 CSR_WRITE_1(sc, SBT_REG_RPC, RPC_PCRRT); in sbt_read_packet()
314 CSR_WRITE_1(sc, SBT_REG_RPC, 0); in sbt_read_packet()
336 CSR_WRITE_1(sc, SBT_REG_ICLR, status); in sbt_intr()
/dports/emulators/gxemul/gxemul-0.6.3/src/include/thirdparty/
H A Drtl81x9reg.h780 #define CSR_WRITE_1(sc, csr, val) \ macro
791 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
794 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))