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Searched refs:CTL_RDY (Results 1 – 15 of 15) sorted by relevance

/dports/emulators/vmips/vmips-1.5.1/test_code/vmips.misc-tests/
H A Dclocker.S21 andi k1, k1, CTL_RDY /* Check the ready bit. */
28 andi k1, k1, CTL_RDY /* Is the display ready? */
40 andi k1, k1, CTL_RDY /* Is the keyboard ready? */
H A Decho.c6 #define IS_READY(ctrl) (((*(ctrl)) & CTL_RDY) != 0)
/dports/emulators/vmips/vmips-1.5.1/
H A Dspimconsole.cc114 word |= CTL_RDY; in fetch_word()
138 word |= CTL_RDY; in fetch_word()
H A Ddevreg.h30 #define CTL_RDY 0x00000001 macro
H A Dclockdev.h81 READY = CTL_RDY
H A Dterminalcontroller.h193 READY = CTL_RDY,
H A Dclockdev.cc86 uint32 word = interrupt_enabled ? CTL_RDY : 0; in fetch_word()
/dports/emulators/vmips/vmips-1.5.1/test_code/vmips.outcheck/
H A Dhello2.c6 #define IS_READY(ctrl) (((*(ctrl)) & CTL_RDY) != 0)
H A Dhello.c6 #define IS_READY(ctrl) (((*(ctrl)) & CTL_RDY) != 0)
H A Dpoke2.S12 andi $2, $2, CTL_RDY
H A Dsb-print.S26 andi t0, t0, CTL_RDY
/dports/emulators/vmips/vmips-1.5.1/test_code/vmips.regcheck/
H A Dhandler5.S38 andi k1, k1, CTL_RDY /* Check the ready bit. */
/dports/emulators/vmips/vmips-1.5.1/sample_code/xmboot/
H A Dserial.c21 return (((*(ctrl)) & CTL_RDY) != 0); in spim_console_is_ready()
/dports/emulators/vmips/vmips-1.5.1/doc/
H A Dvmips.texi1115 ready bit (@code{CTL_RDY} is defined as 0x00000001). All other bits in the
H A Dvmips.info1583 the device ready bit (`CTL_RDY' is defined as 0x00000001). All other