/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUPostLegalizerCombiner.cpp | 216 Register CvtSrc = MatchInfo.CvtVal; in applyCvtF32UByteN() local 220 CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0); in applyCvtF32UByteN() 224 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
|
H A D | AMDGPUISelLowering.cpp | 3812 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3813 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3816 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine() 3824 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine() 3828 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3830 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3833 CvtSrc.getOperand(0), N0.getOperand(1)); in performFNegCombine() 3840 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
|
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AMDGPU/ |
H A D | AMDGPUPostLegalizerCombiner.cpp | 216 Register CvtSrc = MatchInfo.CvtVal; in applyCvtF32UByteN() local 220 CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0); in applyCvtF32UByteN() 224 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
|
H A D | AMDGPUISelLowering.cpp | 3812 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3813 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3816 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine() 3824 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine() 3828 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3830 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3833 CvtSrc.getOperand(0), N0.getOperand(1)); in performFNegCombine() 3840 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
|
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUPostLegalizerCombiner.cpp | 236 Register CvtSrc = MatchInfo.CvtVal; in applyCvtF32UByteN() local 240 CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0); in applyCvtF32UByteN() 244 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
|
H A D | AMDGPUISelLowering.cpp | 3802 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3803 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3806 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine() 3814 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine() 3818 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3820 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3823 CvtSrc.getOperand(0), N0.getOperand(1)); in performFNegCombine() 3830 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
|
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUPostLegalizerCombiner.cpp | 238 Register CvtSrc = MatchInfo.CvtVal; in applyCvtF32UByteN() local 242 CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0); in applyCvtF32UByteN() 246 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
|
H A D | AMDGPUISelLowering.cpp | 3922 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3923 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3926 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine() 3934 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine() 3938 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3940 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3943 CvtSrc.getOperand(0), N0.getOperand(1)); in performFNegCombine() 3950 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
|
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/ |
H A D | AMDGPUPostLegalizerCombiner.cpp | 238 Register CvtSrc = MatchInfo.CvtVal; in applyCvtF32UByteN() local 242 CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0); in applyCvtF32UByteN() 246 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
|
H A D | AMDGPUISelLowering.cpp | 3922 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3923 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3926 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine() 3934 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine() 3938 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3940 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3943 CvtSrc.getOperand(0), N0.getOperand(1)); in performFNegCombine() 3950 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
|
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUPostLegalizerCombiner.cpp | 236 Register CvtSrc = MatchInfo.CvtVal; in applyCvtF32UByteN() local 240 CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0); in applyCvtF32UByteN() 244 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
|
H A D | AMDGPUISelLowering.cpp | 3805 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3806 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3809 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine() 3817 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine() 3821 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3823 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3826 CvtSrc.getOperand(0), N0.getOperand(1)); in performFNegCombine() 3833 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
|
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUPostLegalizerCombiner.cpp | 238 Register CvtSrc = MatchInfo.CvtVal; in applyCvtF32UByteN() local 242 CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0); in applyCvtF32UByteN() 246 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
|
H A D | AMDGPUISelLowering.cpp | 3922 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3923 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3926 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine() 3934 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine() 3938 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3940 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3943 CvtSrc.getOperand(0), N0.getOperand(1)); in performFNegCombine() 3950 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
|
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUPostLegalizerCombiner.cpp | 238 Register CvtSrc = MatchInfo.CvtVal; in applyCvtF32UByteN() local 242 CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0); in applyCvtF32UByteN() 246 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
|
H A D | AMDGPUISelLowering.cpp | 3925 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3926 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3929 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine() 3937 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine() 3941 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3943 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3946 CvtSrc.getOperand(0), N0.getOperand(1)); in performFNegCombine() 3953 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
|
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUPostLegalizerCombiner.cpp | 238 Register CvtSrc = MatchInfo.CvtVal; in applyCvtF32UByteN() local 242 CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0); in applyCvtF32UByteN() 246 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
|
H A D | AMDGPUISelLowering.cpp | 3922 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3923 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3926 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine() 3934 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine() 3938 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3940 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3943 CvtSrc.getOperand(0), N0.getOperand(1)); in performFNegCombine() 3950 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
|
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUPostLegalizerCombiner.cpp | 236 Register CvtSrc = MatchInfo.CvtVal; in applyCvtF32UByteN() local 240 CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0); in applyCvtF32UByteN() 244 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
|
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUPostLegalizerCombiner.cpp | 238 Register CvtSrc = MatchInfo.CvtVal; in applyCvtF32UByteN() local 242 CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0); in applyCvtF32UByteN() 246 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
|
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 3604 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3605 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3608 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine() 3616 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine() 3620 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3622 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3625 CvtSrc.getOperand(0), N0.getOperand(1)); in performFNegCombine() 3632 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
|
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 3815 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3816 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3819 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine() 3827 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine() 3831 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3833 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3836 CvtSrc.getOperand(0), N0.getOperand(1)); in performFNegCombine() 3843 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
|
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 3815 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3816 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3819 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine() 3827 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine() 3831 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3833 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3836 CvtSrc.getOperand(0), N0.getOperand(1)); in performFNegCombine() 3843 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
|
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 3815 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3816 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3819 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine() 3827 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine() 3831 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3833 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3836 CvtSrc.getOperand(0), N0.getOperand(1)); in performFNegCombine() 3843 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
|
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 3695 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3696 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3699 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine() 3707 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine() 3711 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local 3713 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine() 3716 CvtSrc.getOperand(0), N0.getOperand(1)); in performFNegCombine() 3723 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
|