Home
last modified time | relevance | path

Searched refs:DB0_ADC_DCLK_P (Results 1 – 3 of 3) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/
H A Dx300.v116 input DB0_ADC_DCLK_P, input DB0_ADC_DCLK_N, port
574 .adc_clk_p(DB0_ADC_DCLK_P), .adc_clk_n(DB0_ADC_DCLK_N),
H A Dx300.xdc72 set_property PACKAGE_PIN L25 [get_ports DB0_ADC_DCLK_P]
H A Dtiming.xdc12 …lock -name DB0_ADC_DCLK -period 5.000 -waveform {0.000 2.500} [get_ports DB0_ADC_DCLK_P]