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Searched refs:DCACHELINE_SIZE (Results 1 – 25 of 56) sorted by relevance

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/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()
/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()

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