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/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/tcg/
H A Dtcg-opc.h24 #ifndef DEF2
30 DEF2(nop, 0, 0, 0, 0)
31 DEF2(nop1, 0, 0, 1, 0)
32 DEF2(nop2, 0, 0, 2, 0)
33 DEF2(nop3, 0, 0, 3, 0)
36 DEF2(discard, 1, 0, 0, 0)
43 DEF2(mov_i32, 1, 1, 0, 0)
50 DEF2(ld_i32, 1, 1, 1, 0)
55 DEF2(add_i32, 1, 2, 0, 0)
68 DEF2(or_i32, 1, 2, 0, 0)
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/tools/testing/selftests/ftrace/test.d/kprobe/
H A Dkprobe_multiprobe.tc12 DEF2="p:$EVENT_NAME $SYM2"
16 echo $DEF2 >> kprobe_events
18 cat kprobe_events | grep "$DEF2"
26 echo $DEF2 >> kprobe_events
29 cat kprobe_events | grep "$DEF2"
/dports/multimedia/libv4l/linux-5.13-rc2/tools/testing/selftests/ftrace/test.d/kprobe/
H A Dkprobe_multiprobe.tc12 DEF2="p:$EVENT_NAME $SYM2"
16 echo $DEF2 >> kprobe_events
18 cat kprobe_events | grep "$DEF2"
26 echo $DEF2 >> kprobe_events
29 cat kprobe_events | grep "$DEF2"
/dports/multimedia/v4l-utils/linux-5.13-rc2/tools/testing/selftests/ftrace/test.d/kprobe/
H A Dkprobe_multiprobe.tc12 DEF2="p:$EVENT_NAME $SYM2"
16 echo $DEF2 >> kprobe_events
18 cat kprobe_events | grep "$DEF2"
26 echo $DEF2 >> kprobe_events
29 cat kprobe_events | grep "$DEF2"
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-freeze.mir246 ; CHECK: [[DEF2:%[0-9]+]]:_(s1024) = G_IMPLICIT_DEF
249 …DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024)…
431 ; CHECK: [[DEF2:%[0-9]+]]:_(<16 x s32>) = G_IMPLICIT_DEF
435 …DEF2]](<16 x s32>), [[DEF2]](<16 x s32>), [[DEF2]](<16 x s32>), [[DEF2]](<16 x s32>), [[DEF2]](<16…
577 ; CHECK: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
578 ; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[EXTRACT]](<3 x s16>), 0
581 ; CHECK: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[EXTRACT1]](<3 x s16>), 0
632 ; CHECK: [[DEF2:%[0-9]+]]:_(<6 x s16>) = G_IMPLICIT_DEF
633 ; CHECK: [[INSERT:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[DEF2]], [[EXTRACT]](<5 x s16>), 0
636 ; CHECK: [[INSERT1:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[DEF2]], [[EXTRACT1]](<5 x s16>), 0
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-freeze.mir246 ; CHECK: [[DEF2:%[0-9]+]]:_(s1024) = G_IMPLICIT_DEF
249 …DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024)…
431 ; CHECK: [[DEF2:%[0-9]+]]:_(<16 x s32>) = G_IMPLICIT_DEF
435 …DEF2]](<16 x s32>), [[DEF2]](<16 x s32>), [[DEF2]](<16 x s32>), [[DEF2]](<16 x s32>), [[DEF2]](<16…
577 ; CHECK: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
578 ; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[EXTRACT]](<3 x s16>), 0
581 ; CHECK: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[EXTRACT1]](<3 x s16>), 0
632 ; CHECK: [[DEF2:%[0-9]+]]:_(<6 x s16>) = G_IMPLICIT_DEF
633 ; CHECK: [[INSERT:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[DEF2]], [[EXTRACT]](<5 x s16>), 0
636 ; CHECK: [[INSERT1:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[DEF2]], [[EXTRACT1]](<5 x s16>), 0
/dports/lang/gcc48/gcc-4.8.5/gcc/testsuite/gcc.target/aarch64/
H A Dvect-fp.x20 #define DEF2(fname, type, op) \ macro
35 DEF2 (fname, F32, op) \
36 DEF2 (fname, F64, op)
43 DEF2 (abs, F32, fabsf)
44 DEF2 (abs, F64, fabs)
/dports/devel/mingw32-gcc/gcc-4.8.1/gcc/testsuite/gcc.target/aarch64/
H A Dvect-fp.x20 #define DEF2(fname, type, op) \ macro
35 DEF2 (fname, F32, op) \
36 DEF2 (fname, F64, op)
43 DEF2 (abs, F32, fabsf)
44 DEF2 (abs, F64, fabs)
/dports/math/rocs/rocs-21.12.3/libgraphtheory/fileformats/dot/autotests/testfiles/directed/
H A Djcctree.gv6 SPEC -> DEF2;
11 DEF2 -> ID2;
12 DEF2 -> SET2;
13 DEF2 -> SC2;
26 DEF2 [label=DEF];
/dports/graphics/graphviz/graphviz-2.44.1/graphs/directed/
H A Djcctree.gv6 SPEC -> DEF2;
11 DEF2 -> ID2;
12 DEF2 -> SET2;
13 DEF2 -> SC2;
26 DEF2 [label=DEF];
/dports/graphics/graphviz/graphviz-2.44.1/rtest/graphs/
H A Djcctree.gv6 SPEC -> DEF2;
11 DEF2 -> ID2;
12 DEF2 -> SET2;
13 DEF2 -> SC2;
26 DEF2 [label=DEF];
/dports/graphics/py-pydotplus/pydotplus-2.0.2/test/graphs/
H A Djcctree.dot6 SPEC -> DEF2;
11 DEF2 -> ID2;
12 DEF2 -> SET2;
13 DEF2 -> SC2;
26 DEF2 [label=DEF];
/dports/graphics/py-pydot/pydot-1.4.2/test/graphs/
H A Djcctree.dot6 SPEC -> DEF2;
11 DEF2 -> ID2;
12 DEF2 -> SET2;
13 DEF2 -> SC2;
26 DEF2 [label=DEF];
/dports/lang/gcc6-aux/gcc-6-20180516/gcc/testsuite/gcc.target/aarch64/
H A Dvect-fp.x30 #define DEF2(fname, type, op) \ macro
49 DEF2 (fname, F32, op) \
50 DEF2 (fname, F64, op)
57 DEF2 (abs, F32, fabsf)
58 DEF2 (abs, F64, fabs)
/dports/lang/gcc8/gcc-8.5.0/gcc/testsuite/gcc.target/aarch64/
H A Dvect-fp.x30 #define DEF2(fname, type, op) \ macro
49 DEF2 (fname, F32, op) \
50 DEF2 (fname, F64, op)
57 DEF2 (abs, F32, fabsf)
58 DEF2 (abs, F64, fabs)
/dports/lang/gcc10/gcc-10.3.0/gcc/testsuite/gcc.target/aarch64/
H A Dvect-fp.x30 #define DEF2(fname, type, op) \ macro
49 DEF2 (fname, F32, op) \
50 DEF2 (fname, F64, op)
57 DEF2 (abs, F32, fabsf)
58 DEF2 (abs, F64, fabs)
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/
H A Dvect-fp.x30 #define DEF2(fname, type, op) \ macro
49 DEF2 (fname, F32, op) \
50 DEF2 (fname, F64, op)
57 DEF2 (abs, F32, fabsf)
58 DEF2 (abs, F64, fabs)
/dports/lang/gcc11/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/
H A Dvect-fp.x30 #define DEF2(fname, type, op) \ macro
49 DEF2 (fname, F32, op) \
50 DEF2 (fname, F64, op)
57 DEF2 (abs, F32, fabsf)
58 DEF2 (abs, F64, fabs)
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/
H A Dvect-fp.x30 #define DEF2(fname, type, op) \ macro
49 DEF2 (fname, F32, op) \
50 DEF2 (fname, F64, op)
57 DEF2 (abs, F32, fabsf)
58 DEF2 (abs, F64, fabs)
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/
H A Dvect-fp.x30 #define DEF2(fname, type, op) \ macro
49 DEF2 (fname, F32, op) \
50 DEF2 (fname, F64, op)
57 DEF2 (abs, F32, fabsf)
58 DEF2 (abs, F64, fabs)
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/testsuite/gcc.target/aarch64/
H A Dvect-fp.x30 #define DEF2(fname, type, op) \ macro
49 DEF2 (fname, F32, op) \
50 DEF2 (fname, F64, op)
57 DEF2 (abs, F32, fabsf)
58 DEF2 (abs, F64, fabs)
/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/testsuite/gcc.target/aarch64/
H A Dvect-fp.x30 #define DEF2(fname, type, op) \ macro
49 DEF2 (fname, F32, op) \
50 DEF2 (fname, F64, op)
57 DEF2 (abs, F32, fabsf)
58 DEF2 (abs, F64, fabs)
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/testsuite/gcc.target/aarch64/
H A Dvect-fp.x30 #define DEF2(fname, type, op) \ macro
49 DEF2 (fname, F32, op) \
50 DEF2 (fname, F64, op)
57 DEF2 (abs, F32, fabsf)
58 DEF2 (abs, F64, fabs)
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/
H A Dvect-fp.x30 #define DEF2(fname, type, op) \ macro
49 DEF2 (fname, F32, op) \
50 DEF2 (fname, F64, op)
57 DEF2 (abs, F32, fabsf)
58 DEF2 (abs, F64, fabs)
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/testsuite/gcc.target/aarch64/
H A Dvect-fp.x30 #define DEF2(fname, type, op) \ macro
49 DEF2 (fname, F32, op) \
50 DEF2 (fname, F64, op)
57 DEF2 (abs, F32, fabsf)
58 DEF2 (abs, F64, fabs)

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