| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
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| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
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| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
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| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
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| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
|
| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
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| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
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| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
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| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
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| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/board/freescale/lx2160a/ |
| H A D | eth_lx2160ardb.c | 67 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; in board_eth_init()
72 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
132 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in board_eth_init()
192 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); in fdt_fixup_board_phy()
|