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Searched refs:DEFINE_PROP_INT32 (Results 1 – 25 of 235) sorted by relevance

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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/rdma/vmw/
H A Dpvrdma_main.c44 DEFINE_PROP_INT32("dev-caps-max-qp", PVRDMADev, dev_attr.max_qp, MAX_QP),
45 DEFINE_PROP_INT32("dev-caps-max-sge", PVRDMADev, dev_attr.max_sge, MAX_SGE),
46 DEFINE_PROP_INT32("dev-caps-max-cq", PVRDMADev, dev_attr.max_cq, MAX_CQ),
47 DEFINE_PROP_INT32("dev-caps-max-mr", PVRDMADev, dev_attr.max_mr, MAX_MR),
48 DEFINE_PROP_INT32("dev-caps-max-pd", PVRDMADev, dev_attr.max_pd, MAX_PD),
49 DEFINE_PROP_INT32("dev-caps-qp-rd-atom", PVRDMADev, dev_attr.max_qp_rd_atom,
51 DEFINE_PROP_INT32("dev-caps-max-qp-init-rd-atom", PVRDMADev,
53 DEFINE_PROP_INT32("dev-caps-max-ah", PVRDMADev, dev_attr.max_ah, MAX_AH),
/dports/emulators/qemu42/qemu-4.2.1/hw/rdma/vmw/
H A Dpvrdma_main.c46 DEFINE_PROP_INT32("dev-caps-max-qp", PVRDMADev, dev_attr.max_qp, MAX_QP),
47 DEFINE_PROP_INT32("dev-caps-max-cq", PVRDMADev, dev_attr.max_cq, MAX_CQ),
48 DEFINE_PROP_INT32("dev-caps-max-mr", PVRDMADev, dev_attr.max_mr, MAX_MR),
49 DEFINE_PROP_INT32("dev-caps-max-pd", PVRDMADev, dev_attr.max_pd, MAX_PD),
50 DEFINE_PROP_INT32("dev-caps-qp-rd-atom", PVRDMADev, dev_attr.max_qp_rd_atom,
52 DEFINE_PROP_INT32("dev-caps-max-qp-init-rd-atom", PVRDMADev,
54 DEFINE_PROP_INT32("dev-caps-max-ah", PVRDMADev, dev_attr.max_ah, MAX_AH),
55 DEFINE_PROP_INT32("dev-caps-max-srq", PVRDMADev, dev_attr.max_srq, MAX_SRQ),
/dports/emulators/qemu/qemu-6.2.0/hw/rdma/vmw/
H A Dpvrdma_main.c47 DEFINE_PROP_INT32("dev-caps-max-qp", PVRDMADev, dev_attr.max_qp, MAX_QP),
48 DEFINE_PROP_INT32("dev-caps-max-cq", PVRDMADev, dev_attr.max_cq, MAX_CQ),
49 DEFINE_PROP_INT32("dev-caps-max-mr", PVRDMADev, dev_attr.max_mr, MAX_MR),
50 DEFINE_PROP_INT32("dev-caps-max-pd", PVRDMADev, dev_attr.max_pd, MAX_PD),
51 DEFINE_PROP_INT32("dev-caps-qp-rd-atom", PVRDMADev, dev_attr.max_qp_rd_atom,
53 DEFINE_PROP_INT32("dev-caps-max-qp-init-rd-atom", PVRDMADev,
55 DEFINE_PROP_INT32("dev-caps-max-ah", PVRDMADev, dev_attr.max_ah, MAX_AH),
56 DEFINE_PROP_INT32("dev-caps-max-srq", PVRDMADev, dev_attr.max_srq, MAX_SRQ),
/dports/emulators/qemu5/qemu-5.2.0/hw/rdma/vmw/
H A Dpvrdma_main.c46 DEFINE_PROP_INT32("dev-caps-max-qp", PVRDMADev, dev_attr.max_qp, MAX_QP),
47 DEFINE_PROP_INT32("dev-caps-max-cq", PVRDMADev, dev_attr.max_cq, MAX_CQ),
48 DEFINE_PROP_INT32("dev-caps-max-mr", PVRDMADev, dev_attr.max_mr, MAX_MR),
49 DEFINE_PROP_INT32("dev-caps-max-pd", PVRDMADev, dev_attr.max_pd, MAX_PD),
50 DEFINE_PROP_INT32("dev-caps-qp-rd-atom", PVRDMADev, dev_attr.max_qp_rd_atom,
52 DEFINE_PROP_INT32("dev-caps-max-qp-init-rd-atom", PVRDMADev,
54 DEFINE_PROP_INT32("dev-caps-max-ah", PVRDMADev, dev_attr.max_ah, MAX_AH),
55 DEFINE_PROP_INT32("dev-caps-max-srq", PVRDMADev, dev_attr.max_srq, MAX_SRQ),
/dports/emulators/qemu60/qemu-6.0.0/hw/rdma/vmw/
H A Dpvrdma_main.c47 DEFINE_PROP_INT32("dev-caps-max-qp", PVRDMADev, dev_attr.max_qp, MAX_QP),
48 DEFINE_PROP_INT32("dev-caps-max-cq", PVRDMADev, dev_attr.max_cq, MAX_CQ),
49 DEFINE_PROP_INT32("dev-caps-max-mr", PVRDMADev, dev_attr.max_mr, MAX_MR),
50 DEFINE_PROP_INT32("dev-caps-max-pd", PVRDMADev, dev_attr.max_pd, MAX_PD),
51 DEFINE_PROP_INT32("dev-caps-qp-rd-atom", PVRDMADev, dev_attr.max_qp_rd_atom,
53 DEFINE_PROP_INT32("dev-caps-max-qp-init-rd-atom", PVRDMADev,
55 DEFINE_PROP_INT32("dev-caps-max-ah", PVRDMADev, dev_attr.max_ah, MAX_AH),
56 DEFINE_PROP_INT32("dev-caps-max-srq", PVRDMADev, dev_attr.max_srq, MAX_SRQ),
/dports/emulators/qemu-utils/qemu-4.2.1/hw/rdma/vmw/
H A Dpvrdma_main.c46 DEFINE_PROP_INT32("dev-caps-max-qp", PVRDMADev, dev_attr.max_qp, MAX_QP),
47 DEFINE_PROP_INT32("dev-caps-max-cq", PVRDMADev, dev_attr.max_cq, MAX_CQ),
48 DEFINE_PROP_INT32("dev-caps-max-mr", PVRDMADev, dev_attr.max_mr, MAX_MR),
49 DEFINE_PROP_INT32("dev-caps-max-pd", PVRDMADev, dev_attr.max_pd, MAX_PD),
50 DEFINE_PROP_INT32("dev-caps-qp-rd-atom", PVRDMADev, dev_attr.max_qp_rd_atom,
52 DEFINE_PROP_INT32("dev-caps-max-qp-init-rd-atom", PVRDMADev,
54 DEFINE_PROP_INT32("dev-caps-max-ah", PVRDMADev, dev_attr.max_ah, MAX_AH),
55 DEFINE_PROP_INT32("dev-caps-max-srq", PVRDMADev, dev_attr.max_srq, MAX_SRQ),
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/rdma/vmw/
H A Dpvrdma_main.c47 DEFINE_PROP_INT32("dev-caps-max-qp", PVRDMADev, dev_attr.max_qp, MAX_QP),
48 DEFINE_PROP_INT32("dev-caps-max-cq", PVRDMADev, dev_attr.max_cq, MAX_CQ),
49 DEFINE_PROP_INT32("dev-caps-max-mr", PVRDMADev, dev_attr.max_mr, MAX_MR),
50 DEFINE_PROP_INT32("dev-caps-max-pd", PVRDMADev, dev_attr.max_pd, MAX_PD),
51 DEFINE_PROP_INT32("dev-caps-qp-rd-atom", PVRDMADev, dev_attr.max_qp_rd_atom,
53 DEFINE_PROP_INT32("dev-caps-max-qp-init-rd-atom", PVRDMADev,
55 DEFINE_PROP_INT32("dev-caps-max-ah", PVRDMADev, dev_attr.max_ah, MAX_AH),
56 DEFINE_PROP_INT32("dev-caps-max-srq", PVRDMADev, dev_attr.max_srq, MAX_SRQ),
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/rdma/vmw/
H A Dpvrdma_main.c46 DEFINE_PROP_INT32("dev-caps-max-qp", PVRDMADev, dev_attr.max_qp, MAX_QP),
47 DEFINE_PROP_INT32("dev-caps-max-cq", PVRDMADev, dev_attr.max_cq, MAX_CQ),
48 DEFINE_PROP_INT32("dev-caps-max-mr", PVRDMADev, dev_attr.max_mr, MAX_MR),
49 DEFINE_PROP_INT32("dev-caps-max-pd", PVRDMADev, dev_attr.max_pd, MAX_PD),
50 DEFINE_PROP_INT32("dev-caps-qp-rd-atom", PVRDMADev, dev_attr.max_qp_rd_atom,
52 DEFINE_PROP_INT32("dev-caps-max-qp-init-rd-atom", PVRDMADev,
54 DEFINE_PROP_INT32("dev-caps-max-ah", PVRDMADev, dev_attr.max_ah, MAX_AH),
55 DEFINE_PROP_INT32("dev-caps-max-srq", PVRDMADev, dev_attr.max_srq, MAX_SRQ),
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/rdma/vmw/
H A Dpvrdma_main.c46 DEFINE_PROP_INT32("dev-caps-max-qp", PVRDMADev, dev_attr.max_qp, MAX_QP),
47 DEFINE_PROP_INT32("dev-caps-max-cq", PVRDMADev, dev_attr.max_cq, MAX_CQ),
48 DEFINE_PROP_INT32("dev-caps-max-mr", PVRDMADev, dev_attr.max_mr, MAX_MR),
49 DEFINE_PROP_INT32("dev-caps-max-pd", PVRDMADev, dev_attr.max_pd, MAX_PD),
50 DEFINE_PROP_INT32("dev-caps-qp-rd-atom", PVRDMADev, dev_attr.max_qp_rd_atom,
52 DEFINE_PROP_INT32("dev-caps-max-qp-init-rd-atom", PVRDMADev,
54 DEFINE_PROP_INT32("dev-caps-max-ah", PVRDMADev, dev_attr.max_ah, MAX_AH),
55 DEFINE_PROP_INT32("dev-caps-max-srq", PVRDMADev, dev_attr.max_srq, MAX_SRQ),
/dports/emulators/qemu42/qemu-4.2.1/hw/dma/
H A Di8257.c583 DEFINE_PROP_INT32("base", I8257State, base, 0x00),
584 DEFINE_PROP_INT32("page-base", I8257State, page_base, 0x80),
585 DEFINE_PROP_INT32("pageh-base", I8257State, pageh_base, 0x480),
586 DEFINE_PROP_INT32("dshift", I8257State, dshift, 0),
/dports/emulators/qemu/qemu-6.2.0/hw/dma/
H A Di8257.c589 DEFINE_PROP_INT32("base", I8257State, base, 0x00),
590 DEFINE_PROP_INT32("page-base", I8257State, page_base, 0x80),
591 DEFINE_PROP_INT32("pageh-base", I8257State, pageh_base, 0x480),
592 DEFINE_PROP_INT32("dshift", I8257State, dshift, 0),
/dports/emulators/qemu60/qemu-6.0.0/hw/dma/
H A Di8257.c589 DEFINE_PROP_INT32("base", I8257State, base, 0x00),
590 DEFINE_PROP_INT32("page-base", I8257State, page_base, 0x80),
591 DEFINE_PROP_INT32("pageh-base", I8257State, pageh_base, 0x480),
592 DEFINE_PROP_INT32("dshift", I8257State, dshift, 0),
/dports/emulators/qemu-utils/qemu-4.2.1/hw/dma/
H A Di8257.c583 DEFINE_PROP_INT32("base", I8257State, base, 0x00),
584 DEFINE_PROP_INT32("page-base", I8257State, page_base, 0x80),
585 DEFINE_PROP_INT32("pageh-base", I8257State, pageh_base, 0x480),
586 DEFINE_PROP_INT32("dshift", I8257State, dshift, 0),
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/dma/
H A Di8257.c578 DEFINE_PROP_INT32("base", I8257State, base, 0x00),
579 DEFINE_PROP_INT32("page-base", I8257State, page_base, 0x80),
580 DEFINE_PROP_INT32("pageh-base", I8257State, pageh_base, 0x480),
581 DEFINE_PROP_INT32("dshift", I8257State, dshift, 0),
/dports/emulators/qemu5/qemu-5.2.0/hw/dma/
H A Di8257.c589 DEFINE_PROP_INT32("base", I8257State, base, 0x00),
590 DEFINE_PROP_INT32("page-base", I8257State, page_base, 0x80),
591 DEFINE_PROP_INT32("pageh-base", I8257State, pageh_base, 0x480),
592 DEFINE_PROP_INT32("dshift", I8257State, dshift, 0),
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/dma/
H A Di8257.c590 DEFINE_PROP_INT32("base", I8257State, base, 0x00),
591 DEFINE_PROP_INT32("page-base", I8257State, page_base, 0x80),
592 DEFINE_PROP_INT32("pageh-base", I8257State, pageh_base, 0x480),
593 DEFINE_PROP_INT32("dshift", I8257State, dshift, 0),
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/dma/
H A Di8257.c583 DEFINE_PROP_INT32("base", I8257State, base, 0x00),
584 DEFINE_PROP_INT32("page-base", I8257State, page_base, 0x80),
585 DEFINE_PROP_INT32("pageh-base", I8257State, pageh_base, 0x480),
586 DEFINE_PROP_INT32("dshift", I8257State, dshift, 0),
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/dma/
H A Di8257.c589 DEFINE_PROP_INT32("base", I8257State, base, 0x00),
590 DEFINE_PROP_INT32("page-base", I8257State, page_base, 0x80),
591 DEFINE_PROP_INT32("pageh-base", I8257State, pageh_base, 0x480),
592 DEFINE_PROP_INT32("dshift", I8257State, dshift, 0),
/dports/emulators/qemu42/qemu-4.2.1/hw/misc/
H A Dmips_cmgcr.c215 DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1),
216 DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800),
/dports/emulators/qemu/qemu-6.2.0/hw/misc/
H A Dmips_cmgcr.c215 DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1),
216 DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800),
/dports/emulators/qemu60/qemu-6.0.0/hw/misc/
H A Dmips_cmgcr.c215 DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1),
216 DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800),
/dports/emulators/qemu-utils/qemu-4.2.1/hw/misc/
H A Dmips_cmgcr.c215 DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1),
216 DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800),
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/misc/
H A Dmips_cmgcr.c214 DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1),
215 DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800),
/dports/emulators/qemu5/qemu-5.2.0/hw/misc/
H A Dmips_cmgcr.c215 DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1),
216 DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800),
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/misc/
H A Dmips_cmgcr.c215 DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1),
216 DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800),

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