/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 28 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 30 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 33 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 35 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 36 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 37 DEF_MODE_CLASS (MODE_VECTOR_UFRACT), /* SIMD vectors */ \ 38 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 28 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 30 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 33 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 35 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 36 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 37 DEF_MODE_CLASS (MODE_VECTOR_UFRACT), /* SIMD vectors */ \ 38 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 27 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 28 DEF_MODE_CLASS (MODE_UACCUM), /* unsigned accumulator */ \ 29 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 32 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 34 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 35 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 37 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 28 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 30 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 33 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 35 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 36 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 37 DEF_MODE_CLASS (MODE_VECTOR_UFRACT), /* SIMD vectors */ \ 38 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/lang/gcc11/gcc-11.2.0/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 27 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 28 DEF_MODE_CLASS (MODE_UACCUM), /* unsigned accumulator */ \ 29 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 32 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 34 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 35 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 37 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 28 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 30 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 33 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 35 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 36 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 37 DEF_MODE_CLASS (MODE_VECTOR_UFRACT), /* SIMD vectors */ \ 38 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 28 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 30 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 33 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 35 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 36 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 37 DEF_MODE_CLASS (MODE_VECTOR_UFRACT), /* SIMD vectors */ \ 38 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 27 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 28 DEF_MODE_CLASS (MODE_UACCUM), /* unsigned accumulator */ \ 29 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 32 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 34 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 35 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 37 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/lang/gcc8/gcc-8.5.0/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 28 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 30 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 33 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 35 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 36 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 37 DEF_MODE_CLASS (MODE_VECTOR_UFRACT), /* SIMD vectors */ \ 38 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 27 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 28 DEF_MODE_CLASS (MODE_UACCUM), /* unsigned accumulator */ \ 29 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 32 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 34 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 35 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 37 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/lang/gcc6-aux/gcc-6-20180516/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 28 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 30 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 33 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 34 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 35 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 36 DEF_MODE_CLASS (MODE_VECTOR_UFRACT), /* SIMD vectors */ \ 37 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/lang/gnat_util/gcc-6-20180516/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 28 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 30 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 33 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 34 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 35 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 36 DEF_MODE_CLASS (MODE_VECTOR_UFRACT), /* SIMD vectors */ \ 37 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/lang/gcc9/gcc-9.4.0/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 27 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 28 DEF_MODE_CLASS (MODE_UACCUM), /* unsigned accumulator */ \ 29 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 32 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 34 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 35 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 37 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/devel/avr-gcc/gcc-10.2.0/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 27 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 28 DEF_MODE_CLASS (MODE_UACCUM), /* unsigned accumulator */ \ 29 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 32 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 34 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 35 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 37 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 27 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 28 DEF_MODE_CLASS (MODE_UACCUM), /* unsigned accumulator */ \ 29 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 32 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 34 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 35 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 37 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 27 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 28 DEF_MODE_CLASS (MODE_UACCUM), /* unsigned accumulator */ \ 29 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 32 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 34 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 35 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 37 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/lang/gcc10/gcc-10.3.0/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 27 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 28 DEF_MODE_CLASS (MODE_UACCUM), /* unsigned accumulator */ \ 29 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 32 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 34 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 35 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 37 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 27 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 28 DEF_MODE_CLASS (MODE_UACCUM), /* unsigned accumulator */ \ 29 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 32 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 34 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 35 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 37 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 27 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 29 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 32 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 33 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 34 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 35 DEF_MODE_CLASS (MODE_VECTOR_UFRACT), /* SIMD vectors */ \ 36 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/lang/gcc48/gcc-4.8.5/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 27 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 29 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 32 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 33 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 34 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 35 DEF_MODE_CLASS (MODE_VECTOR_UFRACT), /* SIMD vectors */ \ 36 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/devel/mingw32-gcc/gcc-4.8.1/gcc/ |
H A D | mode-classes.def | 21 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 22 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 23 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 27 DEF_MODE_CLASS (MODE_ACCUM), /* signed accumulator */ \ 29 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 32 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 33 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 34 DEF_MODE_CLASS (MODE_VECTOR_FRACT), /* SIMD vectors */ \ 35 DEF_MODE_CLASS (MODE_VECTOR_UFRACT), /* SIMD vectors */ \ 36 DEF_MODE_CLASS (MODE_VECTOR_ACCUM), /* SIMD vectors */ \ [all …]
|
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gcc/gcc/ |
H A D | mode-classes.def | 23 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 24 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 25 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 26 DEF_MODE_CLASS (MODE_PARTIAL_INT), /* integer with padding bits */ \ 27 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 28 DEF_MODE_CLASS (MODE_COMPLEX_INT), /* complex numbers */ \ 29 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 30 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 31 DEF_MODE_CLASS (MODE_VECTOR_FLOAT)
|
H A D | machmode.h | 36 #define DEF_MODE_CLASS(M) M macro 38 #undef DEF_MODE_CLASS
|
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/gcc-4.1-20060728/gcc/ |
H A D | mode-classes.def | 23 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 24 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 25 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 26 DEF_MODE_CLASS (MODE_PARTIAL_INT), /* integer with padding bits */ \ 27 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 28 DEF_MODE_CLASS (MODE_COMPLEX_INT), /* complex numbers */ \ 29 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 30 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 31 DEF_MODE_CLASS (MODE_VECTOR_FLOAT)
|
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gcc/gcc/ |
H A D | mode-classes.def | 23 DEF_MODE_CLASS (MODE_RANDOM), /* other */ \ 24 DEF_MODE_CLASS (MODE_CC), /* condition code in a register */ \ 25 DEF_MODE_CLASS (MODE_INT), /* integer */ \ 26 DEF_MODE_CLASS (MODE_PARTIAL_INT), /* integer with padding bits */ \ 27 DEF_MODE_CLASS (MODE_FLOAT), /* floating point */ \ 28 DEF_MODE_CLASS (MODE_COMPLEX_INT), /* complex numbers */ \ 29 DEF_MODE_CLASS (MODE_COMPLEX_FLOAT), \ 30 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \ 31 DEF_MODE_CLASS (MODE_VECTOR_FLOAT)
|