| /dports/math/polymake/polymake-4.5/apps/fulton/rules/ |
| H A D | toric_divisor.rules | 55 rule DIVISOR.COEFFICIENTS : RaysPerm.PERMUTATION, RaysPerm.DIVISOR.COEFFICIENTS {
61 rule DIVISOR.SECTION_POLYTOPE.INEQUALITIES : RAYS, DIVISOR.COEFFICIENTS {
68 rule DIVISOR.PRINCIPAL : RAYS, DIVISOR.COEFFICIENTS {
78 rule DIVISOR.NEF : {
85 rule DIVISOR.AMPLE : {
94 rule DIVISOR.CARTIER : {
101 rule DIVISOR.CARTIER : {
119 …rule DIVISOR.Q_CARTIER, DIVISOR.CARTIER_DATA : RAYS, DIVISOR.COEFFICIENTS, MAXIMAL_CONES, LINEALIT…
149 rule DIVISOR.CARTIER : DIVISOR.CARTIER_DATA, MAXIMAL_CONES {
163 rule DIVISOR.BASEPOINT_FREE : DIVISOR.CARTIER_DATA, MAXIMAL_CONES, DIVISOR.SECTION_POLYTOPE {
[all …]
|
| /dports/games/7kaa/7kaa-2.15.4p1/src/imgfun/generic/ |
| H A D | CRC.cpp | 51 ax ^= DIVISOR << 7; in crc8()
53 ax ^= DIVISOR << 6; in crc8()
65 ax ^= DIVISOR; in crc8()
70 ax ^= DIVISOR << 7; in crc8()
72 ax ^= DIVISOR << 6; in crc8()
74 ax ^= DIVISOR << 5; in crc8()
76 ax ^= DIVISOR << 4; in crc8()
78 ax ^= DIVISOR << 3; in crc8()
80 ax ^= DIVISOR << 2; in crc8()
82 ax ^= DIVISOR << 1; in crc8()
[all …]
|
| /dports/games/7kaa/7kaa-2.15.4p1/src/imgfun/x86/ |
| H A D | CRC.asm | 26 DIVISOR = 101001011b define
56 XOR AX, DIVISOR SHL 7
60 XOR AX, DIVISOR SHL 6
64 XOR AX, DIVISOR SHL 5
68 XOR AX, DIVISOR SHL 4
72 XOR AX, DIVISOR SHL 3
76 XOR AX, DIVISOR SHL 2
80 XOR AX, DIVISOR SHL 1
84 XOR AX, DIVISOR
92 XOR AX, DIVISOR SHL 7
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AArch64/ |
| H A D | arm64-neon-mul-div-cte.ll | 5 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #41
6 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].8h, v0.16b, [[DIVISOR]].16b
7 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b
18 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
19 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].4s, v0.8h, [[DIVISOR]].8h
20 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h
33 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].4s, [[TMP]]
35 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s
45 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #121
57 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
[all …]
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AArch64/ |
| H A D | arm64-neon-mul-div-cte.ll | 5 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #41
6 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].8h, v0.16b, [[DIVISOR]].16b
7 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b
18 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
19 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].4s, v0.8h, [[DIVISOR]].8h
20 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h
33 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].4s, [[TMP]]
35 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s
45 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #121
57 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AArch64/ |
| H A D | arm64-neon-mul-div-cte.ll | 5 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #41
6 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].8h, v0.16b, [[DIVISOR]].16b
7 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b
18 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
19 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].4s, v0.8h, [[DIVISOR]].8h
20 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h
33 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].4s, [[TMP]]
35 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s
45 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #121
57 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
[all …]
|
| /dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AArch64/ |
| H A D | arm64-neon-mul-div-cte.ll | 5 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #41
6 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].8h, v0.16b, [[DIVISOR]].16b
7 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b
18 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
19 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].4s, v0.8h, [[DIVISOR]].8h
20 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h
33 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].4s, [[TMP]]
35 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s
45 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #121
57 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
| H A D | arm64-neon-mul-div-cte.ll | 5 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #41
6 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].8h, v0.16b, [[DIVISOR]].16b
7 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b
18 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
19 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].4s, v0.8h, [[DIVISOR]].8h
20 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h
33 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].4s, [[TMP]]
35 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s
45 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #121
57 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AArch64/ |
| H A D | arm64-neon-mul-div-cte.ll | 5 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #41
6 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].8h, v0.16b, [[DIVISOR]].16b
7 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b
18 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
19 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].4s, v0.8h, [[DIVISOR]].8h
20 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h
33 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].4s, [[TMP]]
35 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s
45 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #121
57 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
[all …]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/ |
| H A D | arm64-neon-mul-div-cte.ll | 5 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #41
6 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].8h, v0.16b, [[DIVISOR]].16b
7 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b
18 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
19 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].4s, v0.8h, [[DIVISOR]].8h
20 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h
33 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].4s, [[TMP]]
35 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s
45 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #121
57 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AArch64/ |
| H A D | arm64-neon-mul-div-cte.ll | 5 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #41
6 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].8h, v0.16b, [[DIVISOR]].16b
7 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b
18 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
19 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].4s, v0.8h, [[DIVISOR]].8h
20 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h
33 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].4s, [[TMP]]
35 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s
45 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #121
57 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
| H A D | arm64-neon-mul-div-cte.ll | 5 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #41
6 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].8h, v0.16b, [[DIVISOR]].16b
7 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b
18 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
19 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].4s, v0.8h, [[DIVISOR]].8h
20 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h
33 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].4s, [[TMP]]
35 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s
45 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #121
57 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
[all …]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AArch64/ |
| H A D | arm64-neon-mul-div-cte.ll | 5 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #41
6 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].8h, v0.16b, [[DIVISOR]].16b
7 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b
18 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
19 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].4s, v0.8h, [[DIVISOR]].8h
20 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h
33 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].4s, [[TMP]]
35 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s
45 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #121
57 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
[all …]
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/ |
| H A D | arm64-neon-mul-div-cte.ll | 5 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #41
6 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].8h, v0.16b, [[DIVISOR]].16b
7 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b
18 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
19 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].4s, v0.8h, [[DIVISOR]].8h
20 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h
33 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].4s, [[TMP]]
35 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s
45 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #121
57 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
[all …]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
| H A D | arm64-neon-mul-div-cte.ll | 5 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #41
6 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].8h, v0.16b, [[DIVISOR]].16b
7 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b
18 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
19 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].4s, v0.8h, [[DIVISOR]].8h
20 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h
33 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].4s, [[TMP]]
35 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s
45 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #121
57 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
[all …]
|
| /dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AArch64/ |
| H A D | arm64-neon-mul-div-cte.ll | 5 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #41
6 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].8h, v0.16b, [[DIVISOR]].16b
7 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b
18 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
19 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].4s, v0.8h, [[DIVISOR]].8h
20 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h
33 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].4s, [[TMP]]
35 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s
45 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #121
57 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
[all …]
|
| /dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AArch64/ |
| H A D | arm64-neon-mul-div-cte.ll | 5 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #41
6 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].8h, v0.16b, [[DIVISOR]].16b
7 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b
18 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
19 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].4s, v0.8h, [[DIVISOR]].8h
20 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h
33 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].4s, [[TMP]]
35 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s
45 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #121
57 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
[all …]
|
| /dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AArch64/ |
| H A D | arm64-neon-mul-div-cte.ll | 5 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #41
6 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].8h, v0.16b, [[DIVISOR]].16b
7 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b
18 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
19 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].4s, v0.8h, [[DIVISOR]].8h
20 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h
33 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].4s, [[TMP]]
35 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s
45 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #121
57 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
[all …]
|
| /dports/archivers/libdeflate/libdeflate-1.8/lib/ |
| H A D | adler32_vec_template.h | 80 s1 %= DIVISOR; in FUNCNAME()
81 s2 %= DIVISOR; in FUNCNAME()
102 s1 %= DIVISOR; in FUNCNAME()
103 s2 %= DIVISOR; in FUNCNAME()
112 s1 %= DIVISOR; in FUNCNAME()
113 s2 %= DIVISOR; in FUNCNAME()
|
| /dports/biology/vt/vt-0.57721/lib/libdeflate/lib/ |
| H A D | adler32_vec_template.h | 80 s1 %= DIVISOR; in FUNCNAME()
81 s2 %= DIVISOR; in FUNCNAME()
102 s1 %= DIVISOR; in FUNCNAME()
103 s2 %= DIVISOR; in FUNCNAME()
112 s1 %= DIVISOR; in FUNCNAME()
113 s2 %= DIVISOR; in FUNCNAME()
|
| /dports/biology/plink/plink-ng-79b2df8c/2.0/libdeflate/lib/ |
| H A D | adler32_vec_template.h | 80 s1 %= DIVISOR; in FUNCNAME()
81 s2 %= DIVISOR; in FUNCNAME()
102 s1 %= DIVISOR; in FUNCNAME()
103 s2 %= DIVISOR; in FUNCNAME()
112 s1 %= DIVISOR; in FUNCNAME()
113 s2 %= DIVISOR; in FUNCNAME()
|
| /dports/games/libretro-mame2000/mame2000-libretro-e364a15/src/machine/ |
| H A D | swmathbx.c | 232 static int DIVISOR, DIVIDEND; variable
265 DIVISOR = ((DIVISOR & 0x00ff) | (data<<8)); in WRITE_HANDLER()
276 DIVISOR = ((DIVISOR & 0xff00) | (data)); in WRITE_HANDLER()
278 if (DIVIDEND >= 2*DIVISOR) in WRITE_HANDLER()
281 RESULT = (int)((((long)DIVIDEND<<14)/(long)DIVISOR)); in WRITE_HANDLER()
|
| /dports/java/openjdk11/jdk11u-jdk-11.0.13-8-1/test/hotspot/jtreg/compiler/c2/ |
| H A D | Test6800154.java | 74 static final long DIVISOR; field in Test6800154
82 DIVISOR = value;
111 … throw new InternalError(dividend + " / " + DIVISOR + " failed: " + result + " != " + expected); in run()
115 static long divint(long a) { return a / DIVISOR; } in divint()
116 static long divcomp(long a) { return a / DIVISOR; } in divcomp()
|
| /dports/java/openjdk13/jdk13u-jdk-13.0.10-1-1/test/hotspot/jtreg/compiler/c2/ |
| H A D | Test6800154.java | 74 static final long DIVISOR; field in Test6800154
82 DIVISOR = value;
111 … throw new InternalError(dividend + " / " + DIVISOR + " failed: " + result + " != " + expected); in run()
115 static long divint(long a) { return a / DIVISOR; } in divint()
116 static long divcomp(long a) { return a / DIVISOR; } in divcomp()
|
| /dports/java/openjdk15/jdk15u-jdk-15.0.6-1-1/test/hotspot/jtreg/compiler/c2/ |
| H A D | Test6800154.java | 74 static final long DIVISOR; field in Test6800154
82 DIVISOR = value;
111 … throw new InternalError(dividend + " / " + DIVISOR + " failed: " + result + " != " + expected); in run()
115 static long divint(long a) { return a / DIVISOR; } in divint()
116 static long divcomp(long a) { return a / DIVISOR; } in divcomp()
|