1 2 #ifndef __COMMONREGS_H__ 3 #define __COMMONREGS_H__ 4 5 6 #define FIFO_SIZE 0x1f 7 8 /* IO register offsets. */ 9 #define FIFO_SWAP_NO 0x00 /* FIFO. No byte swap. */ 10 #define FIFO_SWAP_END 0x04 /* FIFO. Swap bytes 3<>0, 2<>1. */ 11 #define FIFO_SWAP_INHW 0x08 /* FIFO. Swap bytes 3<>2, 1<>0. */ 12 #define FIFO_SWAP_HW 0x0c /* FIFO. Swap half-words. */ 13 #define FIFOINFREE 0x40 /* Input FIFO free entry count. */ 14 #define FIFOOUTVALID 0x41 /* Output FIFO valid entry count. */ 15 #define COMM 0x42 /* dual 4 bit communications ports */ 16 #define MEMENDIAN 0x43 /* set byte swapping on PCI mem accesses */ 17 #define INTR 0x44 /* which interrupts occurred */ 18 #define INTREN 0x46 /* enable different interrupts */ 19 #define DEBUGREG 0x48 /* soft resets, RISC hold/single step */ 20 #define LOWWATERMARK 0x49 /* Input FIFO low water mark for interrupt */ 21 #define PCITEST 0x4C /* PCI test */ 22 #define DMACMDPTR 0x50 /* DMA command list pointer */ 23 #define DMA_ADDRESS 0x54 /* DMA data address */ 24 #define DMA_COUNT 0x58 /* DMA remaining transfer count */ 25 #define STATEINDEX 0x60 /* state index info */ 26 #define STATEDATA 0x64 /* state data info */ 27 #define SCRATCH 0x70 /* 16-bit BIOS scratch space */ 28 #define MODEREG 0x72 /* Mode -- to differentiate from old MODE */ 29 #define MODE_ MODEREG 30 #define MODE MODEREG 31 #define BANKSELECT 0x74 /* Local memory to A0000 mapping */ 32 #define BANKSELECT_PHYSADDR ((unsigned long)(0xA0000)) 33 #define CRTCTEST 0x80 /* CRTC test register */ 34 #define CRTCCTL 0x84 /* CRTC mode */ 35 #define CRTCHORZ 0x88 /* CRTC horizontal timing */ 36 #define CRTCVERT 0x8c /* CRTC vertical timing */ 37 #define FRAMEBASEB 0x90 /* Stereoscopic frame base b address */ 38 #define FRAMEBASEA 0x94 /* Frame base A address */ 39 #define CRTCOFFSET 0x98 /* CRTC StrideOffset */ 40 #define CRTCSTATUS 0x9c /* CRTC video scan position */ 41 #define DRAMCTL 0xa0 /* DRAM timing */ 42 #define PALETTE 0xb0 /* Access to DAC */ 43 #define RAMDACBASEADDR 0xb0 /* Access to DAC */ 44 #define DEVICE0 0xc0 /* external device 0 (PLL) */ 45 #define DEVICE1 0xd0 /* external device 1 */ 46 47 /* IO register flag bits */ 48 /* _MASK defined for multi-bit values */ 49 /* _ADDR defined for registers accessible from RISC */ 50 51 /* COMM */ 52 #define SYSSTATUS_MASK 0x0f /* host->RISC comm */ 53 #define SYSSTATUS_SHIFT 0 54 #define RISCSTATUS_MASK 0xf0 /* RISC->host comm r/o */ 55 #define RISCSTATUS_SHIFT 4 56 57 /* MEMENDIAN */ 58 #define MEMENDIAN_NO 0 /* No byte swap. */ 59 #define MEMENDIAN_END 1 /* Swap bytes 3<>0, 2<>1. */ 60 #define MEMENDIAN_INHW 2 /* Swap bytes 3<>2, 1<>0. */ 61 #define MEMENDIAN_HW 3 /* Swap half-words. */ 62 #define MEMENDIAN_MASK 3 63 #define MEMENDIAN_SHIFT 0 64 65 #define DMABUSY 0x80 /* DMA busy r/o */ 66 #define DMACMDPTR_DMABUSY 0x1 /* corresponding bit in other reg */ 67 68 /* INTR */ 69 #define VERTINTR 0x01 /* vert retrace */ 70 #define FIFOLOWINTR 0x02 /* free entries rose above low water */ 71 #define RISCINTR 0x04 /* RISC firmware interrupt */ 72 #define HALTINTR 0x08 /* RISC halted */ 73 #define FIFOERRORINTR 0x10 /* FIFO under/over flow */ 74 #define DMAERRORINTR 0x20 /* PCI error during DMA */ 75 #define DMAINTR 0x40 /* DMA done interrupt */ 76 #define XINTR 0x80 /* external device pass thru intr */ 77 78 /* INTREN */ 79 #define VERTINTREN 0x01 /* vert retrace */ 80 #define FIFOLOWINTREN 0x02 /* free entries rose above low water */ 81 #define RISCINTREN 0x04 /* RISC firmware interrupt */ 82 #define HALTINTREN 0x08 /* RISC halted */ 83 #define FIFOERRORINTREN 0x10 /* FIFO under/over flow */ 84 #define DMAERRORINTREN 0x20 /* PCI error during DMA */ 85 #define DMAINTREN 0x40 /* DMA done interrupt */ 86 #define XINTREN 0x80 /* external device pass thru intr */ 87 88 /* DEBUG */ 89 #define SOFTRESET 0x01 /* soft reset chip */ 90 #define HOLDRISC 0x02 /* stop RISC when set */ 91 #define STEPRISC 0x04 /* single step RISC */ 92 #define DIRECTSCLK 0x08 /* disable internal divide by 2 for sys clk */ 93 #define SOFTVGARESET 0x10 /* assert VGA reset */ 94 #define SOFTXRESET 0x20 /* assert XReset output to ext devices */ 95 96 /* MODE_ register */ 97 #define VESA_MODE 0x01 /* enable 0xA0000 in native mode */ 98 #define VGA_MODE 0x02 /* VGA mode if set else native mode */ 99 #define VGA_32 0x04 /* enable VGA 32 bit accesses */ 100 #define DMA_EN 0x08 /* enable DMA accesses */ 101 102 #define NATIVE_MODE 0 /* not VESA and not VGA */ 103 104 /* DRAM register */ 105 #define DRAMCTL_ADDR 0xffe00500 106 #define DRAMCTL_SLOWPRECHARGE 0x140010 107 #define DRAMCTL_NORMAL 0x140000 108 109 /* CRTC registers */ 110 #define CRTCTEST_ADDR 0xffe00400 111 #define CRTCCTL_ADDR 0xffe00420 112 #define CRTCHORZ_ADDR 0xffe00440 113 #define CRTCVERT_ADDR 0xffe00460 114 #define FRAMEBASEB_ADDR 0xffe00480 115 #define FRAMEBASEA_ADDR 0xffe004a0 116 #define CRTCOFFSET_ADDR 0xffe004c0 117 #define CRTCSTATUS_ADDR 0xffe004e0 118 119 #define CRTCTEST_VIDEOLATENCY_MASK 0x1F 120 #define CRTCTEST_NOTVBLANK 0x10000 121 #define CRTCTEST_VBLANK 0x40000 122 123 #define CRTCCTL_SCRNFMT_MASK 0xF 124 #define CRTCCTL_VIDEOFIFOSIZE128 0x10 125 #define CRTCCTL_ENABLEDDC 0x20 126 #define CRTCCTL_DDCOUTPUT 0x40 127 #define CRTCCTL_DDCDATA 0x80 128 #define CRTCCTL_VSYNCHI 0x100 129 #define CRTCCTL_HSYNCHI 0x200 130 #define CRTCCTL_VSYNCENABLE 0x400 131 #define CRTCCTL_HSYNCENABLE 0x800 132 #define CRTCCTL_VIDEOENABLE 0x1000 133 #define CRTCCTL_STEREOSCOPIC 0x2000 134 #define CRTCCTL_FRAMEDISPLAYED 0x4000 135 #define CRTCCTL_FRAMEBUFFERBGR 0x8000 136 #define CRTCCTL_EVENFRAME 0x10000 137 #define CRTCCTL_LINEDOUBLE 0x20000 138 #define CRTCCTL_FRAMESWITCHED 0x40000 139 140 #define CRTCHORZ_ACTIVE_MASK 0xFF 141 #define CRTCHORZ_ACTIVE_SHIFT 0 142 #define CRTCHORZ_BACKPORCH_MASK 0x7E00 143 #define CRTCHORZ_BACKPORCH_SHIFT 11 144 #define CRTCHORZ_SYNC_MASK 0x1F0000L 145 #define CRTCHORZ_SYNC_SHIFT 16 146 #define CRTCHORZ_FRONTPORCH_MASK 0xE00000L 147 #define CRTCHORZ_FRONTPORCH_SHIFT 20 148 149 #define CRTCVERT_ACTIVE_MASK 0x7FF 150 #define CRTCVERT_BACKPORCH_MASK 0x1F800 151 #define CRTCVERT_SYNC_MASK 0xE0000 152 #define CRTCVERT_FRONTPORCH_MASK 0x03F00000 153 154 #define CRTCOFFSET_MASK 0xFFFF 155 156 #define CRTCSTATUS_HORZCLOCKS_MASK 0xFF 157 #define CRTCSTATUS_HORZ_MASK 0x600 158 #define CRTCSTATUS_HORZ_FPORCH 0x200 159 #define CRTCSTATUS_HORZ_SYNC 0x600 160 #define CRTCSTATUS_HORZ_BPORCH 0x400 161 #define CRTCSTATUS_HORZ_ACTIVE 0x000 162 #define CRTCSTATUS_SCANLINESLEFT_MASK 0x003FF800 163 #define CRTCSTATUS_VERT_MASK 0xC00000 164 #define CRTCSTATUS_VERT_FPORCH 0x400000 165 #define CRTCSTATUS_VERT_SYNC 0xC00000 166 #define CRTCSTATUS_VERT_BPORCH 0x800000 167 #define CRTCSTATUS_VERT_ACTIVE 0x000000 168 169 /* RAMDAC registers - avail through I/O space */ 170 171 #define DACRAMWRITEADR 0xb0 172 #define DACRAMDATA 0xb1 173 #define DACPIXELMSK 0xb2 174 #define DACRAMREADADR 0xb3 175 #define DACOVSWRITEADR 0xb4 176 #define DACOVSDATA 0xb5 177 #define DACCOMMAND0 0xb6 178 #define DACOVSREADADR 0xb7 179 #define DACCOMMAND1 0xb8 180 #define DACCOMMAND2 0xb9 181 #define DACSTATUS 0xba 182 #define DACCOMMAND3 0xba /* accessed via unlocking/indexing */ 183 #define DACCURSORDATA 0xbb 184 #define DACCURSORXLOW 0xbc 185 #define DACCURSORXHIGH 0xbd 186 #define DACCURSORYLOW 0xbe 187 #define DACCURSORYHIGH 0xbf 188 189 /* values for DACCOMMAND3 */ 190 #define DACCOMMAND3_INIT 0x00 191 #define DAC_CLK_DOUBLER 0x8 192 193 #define PLLDEV DEVICE0 194 195 /* Some state indices */ 196 #define STATEINDEX_IR 128 197 #define STATEINDEX_PC 129 198 #define STATEINDEX_S1 130 199 200 /* PCI configuration registers. */ 201 #define CONFIGIOREG 0xE0000014 202 #define CONFIGENABLE 0xE0000004 203 #ifdef USEROM 204 #define CONFIGROMREG 0xE0000030 205 #endif 206 207 /* Cache parameters. */ 208 #define ICACHESIZE 2048 /* I cache size. */ 209 #define ICACHELINESIZE 32 /* I cache line size. */ 210 #define ICACHE_ONOFF_MASK (((vu32)1<<17)|(1<<3)) 211 #define ICACHE_ON ((0<<17)|(0<<3)) 212 #define ICACHE_OFF (((vu32)1<<17)|(1<<3)) 213 214 215 216 #endif /* __COMMONREGS_H__ */ 217