Searched refs:DMA_STREAM_WIDTH (Results 1 – 3 of 3) sorted by relevance
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ |
H A D | x300_pcie_int.v | 16 … GET_DMA_BUS(parallel_bus, chan_idx) parallel_bus[(DMA_STREAM_WIDTH*(chan_idx+1))-1:(DMA_STREAM_WI… 21 parameter DMA_STREAM_WIDTH = 64, constant 39 input [(NUM_TX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmatx_tdata_iop2, 43 output [(NUM_RX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmarx_tdata_iop2, 50 output [DMA_STREAM_WIDTH-1:0] dmatx_tdata, 56 input [DMA_STREAM_WIDTH-1:0] dmarx_tdata, 166 wire [DMA_STREAM_WIDTH-1:0] dmarx_header; 251 wire [DMA_STREAM_WIDTH-1:0] dmatx_tdata_mux; 306 axi_fifo_flop2 #(.WIDTH(DMA_STREAM_WIDTH+1+DMA_RX_DEST_WIDTH)) tx_pipeline_reg ( 324 wire [DMA_STREAM_WIDTH-1:0] dmarx_tdata_mux; [all …]
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H A D | x300.v | 656 localparam DMA_STREAM_WIDTH = `LVFPGA_IFACE_DMA_CHAN_WIDTH; constant 664 wire [DMA_STREAM_WIDTH-1:0] dmatx_tdata, dmarx_tdata, pcii_tdata, pcio_tdata; 685 wire [(NUM_TX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmatx_tdata_iop2; 688 wire [(NUM_RX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmarx_tdata_iop2; 769 .DMA_STREAM_WIDTH(DMA_STREAM_WIDTH), 846 axi_fifo_short #(.WIDTH(DMA_STREAM_WIDTH+1+DMA_DEST_WIDTH)) pcii_pipeline_srl ( 852 axi_fifo_short #(.WIDTH(DMA_STREAM_WIDTH+1+DMA_DEST_WIDTH)) pcio_pipeline_srl (
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/sim/x300_pcie_int/ |
H A D | x300_pcie_int_tb.sv | 473 .DMA_STREAM_WIDTH (64),
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