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Searched refs:DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS (Results 1 – 20 of 20) sorted by relevance

/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c337 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in psb_intel_crtc_clock_get()
H A Dpsb_intel_reg.h253 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 macro
H A Dcdv_intel_display.c868 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in cdv_intel_crtc_clock_get()
/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm/dist/shared-core/
H A Di915_reg.h412 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c337 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in psb_intel_crtc_clock_get()
H A Dpsb_intel_reg.h253 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 macro
H A Dcdv_intel_display.c868 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in cdv_intel_crtc_clock_get()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c337 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in psb_intel_crtc_clock_get()
H A Dpsb_intel_reg.h253 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 macro
H A Dcdv_intel_display.c868 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in cdv_intel_crtc_clock_get()
/dports/x11-drivers/xf86-video-intel/xf86-video-intel-31486f40f8e8f8923ca0799aea84b58799754564/src/legacy/i810/
H A Di810_reg.h982 # define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 macro
/dports/graphics/intel-backlight/intel_backlight_fbsd-a6c0e39/
H A Dintel_reg.h1203 # define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 macro
/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm2/dist/drm/i915/
H A Di915_reg.h1284 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 macro
H A Dintel_display.c8293 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in i9xx_crtc_clock_get()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/i915/
H A Di915_reg.h3487 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/i915/
H A Di915_reg.h3487 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/i915/
H A Di915_reg.h3487 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/i915/display/
H A Dintel_display.c6392 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in i9xx_crtc_clock_get()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/i915/display/
H A Dintel_display.c6392 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in i9xx_crtc_clock_get()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/i915/display/
H A Dintel_display.c6392 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in i9xx_crtc_clock_get()