1 /* 2 * $Id: dmac.h,v 1.4 2005/09/29 11:13:32 telka Exp $ 3 * 4 * H8/3048 DMAC Registers 5 * Copyright (C) 2005 Elcom s.r.o. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the copyright holders nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Written by Branislav Petrovsky <brano111@szm.sk>, 2005. 32 * 33 * Documentation: 34 * [1] Renesas Technology Corp., "Hitachi Single-Chip Microcomputer 35 * H8/3048 Series, H8/3048F-ZTAT Hardware Manual", 36 * Rev. 6.0, 9/3/2002, Order Number: ADE-602-073E 37 * 38 */ 39 40 #ifndef H83048_DMAC_H 41 #define H83048_DMAC_H 42 43 #include <openwince.h> 44 45 #ifndef __ASSEMBLY__ 46 #include <stdint.h> 47 #endif 48 49 /* DMAC registers */ 50 51 #define DMAC_BASE 0xffff20 52 53 #ifndef __ASSEMBLY__ 54 typedef volatile struct DMAC_registers { 55 uint32_t mar0a; 56 uint16_t etcr0a; 57 uint8_t ioar0a; 58 uint8_t dtcr0a; 59 uint32_t mar0b; 60 uint16_t etcr0b; 61 uint8_t ioar0b; 62 uint8_t dtcr0b; 63 uint32_t mar1a; 64 uint16_t etcr1a; 65 uint8_t ioar1a; 66 uint8_t dtcr1a; 67 uint32_t mar1b; 68 uint16_t etcr1b; 69 uint8_t ioar1b; 70 uint8_t dtcr1b; 71 } DMAC_registers_t; 72 73 #define DMAC_pointer ((DMAC_registers_t*) DMAC_BASE) 74 75 #define MAR0A DMAC_pointer->mar0a 76 #define ETCR0A DMAC_pointer->etcr0a 77 #define IOAR0A DMAC_pointer->ioar0a 78 #define DTCR0A DMAC_pointer->dtcr0a 79 #define MAR0B DMAC_pointer->mar0b 80 #define ETCR0B DMAC_pointer->etcr0b 81 #define IOAR0B DMAC_pointer->ioar0b 82 #define DTCR0B DMAC_pointer->dtcr0b 83 #define MAR1A DMAC_pointer->mar1a 84 #define ETCR1A DMAC_pointer->etcr1a 85 #define IOAR1A DMAC_pointer->ioar1a 86 #define DTCR1A DMAC_pointer->dtcr1a 87 #define MAR1B DMAC_pointer->mar1b 88 #define ETCR1B DMAC_pointer->etcr1b 89 #define IOAR1B DMAC_pointer->ioar1b 90 #define DTCR1B DMAC_pointer->dtcr1b 91 #endif /* __ASSEMBLY__ */ 92 93 #define MAR0A_OFFSET 0x00 94 #define ETCR0A_OFFSET 0x04 95 #define IOAR0A_OFFSET 0x06 96 #define DTCR0A_OFFSET 0x07 97 #define MAR0B_OFFSET 0x08 98 #define ETCR0B_OFFSET 0x0c 99 #define IOAR0B_OFFSET 0x0e 100 #define DTCR0B_OFFSET 0x0f 101 #define MAR1A_OFFSET 0x10 102 #define ETCR1A_OFFSET 0x14 103 #define IOAR1A_OFFSET 0x16 104 #define DTCR1A_OFFSET 0x17 105 #define MAR1B_OFFSET 0x18 106 #define ETCR1B_OFFSET 0x1c 107 #define IOAR1B_OFFSET 0x1e 108 #define DTCR1B_OFFSET 0x1f 109 110 /* DTCRA bits - short address mode */ 111 #define DTCRA_DTE bit(7) 112 #define DTCRA_DTSZ bit(6) 113 #define DTCRA_DTID bit(5) 114 #define DTCRA_RPE bit(4) 115 #define DTCRA_DTIE bit(3) 116 #define DTCRA_DTS_MASK bits(2,0) 117 #define DTCRA_DTS(x) bits_val(2,0,x) 118 #define get_DTCRA_DTS(x) bits_get(2,0,x) 119 120 /* DTCRA bits - full address mode */ 121 #define DTCRA_SAID bit(5) 122 #define DTCRA_SAIDE bit(4) 123 #define DTCRA_DTSA_MASK bits(2,0) 124 #define DTCRA_DTSA(x) bits_val(2,0,x) 125 #define get_DTCRA_DTSA(x) bits_get(2,0,x) 126 127 /* DTCRB bits - short address mode */ 128 #define DTCRB_DTE bit(7) 129 #define DTCRB_DTSZ bit(6) 130 #define DTCRB_DTID bit(5) 131 #define DTCRB_RPE bit(4) 132 #define DTCRB_DTIE bit(3) 133 #define DTCRB_DTS_MASK bits(2,0) 134 #define DTCRB_DTS(x) bits_val(2,0,x) 135 #define get_DTCRB_DTS(x) bits_get(2,0,x) 136 137 /* DTCRB bits - full address mode */ 138 #define DTCRB_DAID bit(5) 139 #define DTCRB_DAIDE bit(4) 140 #define DTCRB_TMS bit(3) 141 #define DTCRB_DTSB_MASK bits(2,0) 142 #define DTCRB_DTSB(x) bits_val(2,0,x) 143 #define get_DTCRB_DTSB(x) bits_get(2,0,x) 144 145 #endif /* H83048_DMAC_H */ 146