1 //***************************************************************************** 2 // 3 // Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 4 // 5 // 6 // Redistribution and use in source and binary forms, with or without 7 // modification, are permitted provided that the following conditions 8 // are met: 9 // 10 // Redistributions of source code must retain the above copyright 11 // notice, this list of conditions and the following disclaimer. 12 // 13 // Redistributions in binary form must reproduce the above copyright 14 // notice, this list of conditions and the following disclaimer in the 15 // documentation and/or other materials provided with the 16 // distribution. 17 // 18 // Neither the name of Texas Instruments Incorporated nor the names of 19 // its contributors may be used to endorse or promote products derived 20 // from this software without specific prior written permission. 21 // 22 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 26 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 28 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 // 34 //***************************************************************************** 35 //***************************************************************************** 36 37 #ifndef __HW_DTHE_H__ 38 #define __HW_DTHE_H__ 39 40 //***************************************************************************** 41 // 42 // The following are defines for the DTHE register offsets. 43 // 44 //***************************************************************************** 45 #define DTHE_O_SHA_IM 0x00000810 46 #define DTHE_O_SHA_RIS 0x00000814 47 #define DTHE_O_SHA_MIS 0x00000818 48 #define DTHE_O_SHA_IC 0x0000081C 49 #define DTHE_O_AES_IM 0x00000820 50 #define DTHE_O_AES_RIS 0x00000824 51 #define DTHE_O_AES_MIS 0x00000828 52 #define DTHE_O_AES_IC 0x0000082C 53 #define DTHE_O_DES_IM 0x00000830 54 #define DTHE_O_DES_RIS 0x00000834 55 #define DTHE_O_DES_MIS 0x00000838 56 #define DTHE_O_DES_IC 0x0000083C 57 #define DTHE_O_EIP_CGCFG 0x00000A00 58 #define DTHE_O_EIP_CGREQ 0x00000A04 59 #define DTHE_O_CRC_CTRL 0x00000C00 60 #define DTHE_O_CRC_SEED 0x00000C10 61 #define DTHE_O_CRC_DIN 0x00000C14 62 #define DTHE_O_CRC_RSLT_PP 0x00000C18 63 #define DTHE_O_RAND_KEY0 0x00000F00 64 #define DTHE_O_RAND_KEY1 0x00000F04 65 #define DTHE_O_RAND_KEY2 0x00000F08 66 #define DTHE_O_RAND_KEY3 0x00000F0C 67 68 69 //****************************************************************************** 70 // 71 // The following are defines for the bit fields in the 72 // DTHE_O_SHAMD5_IMST register. 73 // 74 //****************************************************************************** 75 #define DTHE_SHAMD5_IMST_DIN 0x00000004 // Data in: this interrupt is 76 // raised when DMA writes last word 77 // of input data to internal FIFO of 78 // the engine 79 #define DTHE_SHAMD5_IMST_COUT 0x00000002 // Context out: this interrupt is 80 // raised when DMA complets the 81 // output context movement from 82 // internal register 83 #define DTHE_SHAMD5_IMST_CIN 0x00000001 // context in: this interrupt is 84 // raised when DMA complets Context 85 // write to internal register 86 //****************************************************************************** 87 // 88 // The following are defines for the bit fields in the 89 // DTHE_O_SHAMD5_IRIS register. 90 // 91 //****************************************************************************** 92 #define DTHE_SHAMD5_IRIS_DIN 0x00000004 // input Data movement is done 93 #define DTHE_SHAMD5_IRIS_COUT 0x00000002 // Context output is done 94 #define DTHE_SHAMD5_IRIS_CIN 0x00000001 // context input is done 95 //****************************************************************************** 96 // 97 // The following are defines for the bit fields in the 98 // DTHE_O_SHAMD5_IMIS register. 99 // 100 //****************************************************************************** 101 #define DTHE_SHAMD5_IMIS_DIN 0x00000004 // input Data movement is done 102 #define DTHE_SHAMD5_IMIS_COUT 0x00000002 // Context output is done 103 #define DTHE_SHAMD5_IMIS_CIN 0x00000001 // context input is done 104 //****************************************************************************** 105 // 106 // The following are defines for the bit fields in the 107 // DTHE_O_SHAMD5_ICIS register. 108 // 109 //****************************************************************************** 110 #define DTHE_SHAMD5_ICIS_DIN 0x00000004 // Clear “input Data movement done” 111 // flag 112 #define DTHE_SHAMD5_ICIS_COUT 0x00000002 // Clear “Context output done” flag 113 #define DTHE_SHAMD5_ICIS_CIN 0x00000001 // Clear “context input done” flag 114 //****************************************************************************** 115 // 116 // The following are defines for the bit fields in the 117 // DTHE_O_AES_IMST register. 118 // 119 //****************************************************************************** 120 #define DTHE_AES_IMST_DOUT 0x00000008 // Data out: this interrupt is 121 // raised when DMA finishes writing 122 // last word of the process result 123 #define DTHE_AES_IMST_DIN 0x00000004 // Data in: this interrupt is 124 // raised when DMA writes last word 125 // of input data to internal FIFO of 126 // the engine 127 #define DTHE_AES_IMST_COUT 0x00000002 // Context out: this interrupt is 128 // raised when DMA complets the 129 // output context movement from 130 // internal register 131 #define DTHE_AES_IMST_CIN 0x00000001 // context in: this interrupt is 132 // raised when DMA complets Context 133 // write to internal register 134 //****************************************************************************** 135 // 136 // The following are defines for the bit fields in the 137 // DTHE_O_AES_IRIS register. 138 // 139 //****************************************************************************** 140 #define DTHE_AES_IRIS_DOUT 0x00000008 // Output Data movement is done 141 #define DTHE_AES_IRIS_DIN 0x00000004 // input Data movement is done 142 #define DTHE_AES_IRIS_COUT 0x00000002 // Context output is done 143 #define DTHE_AES_IRIS_CIN 0x00000001 // context input is done 144 //****************************************************************************** 145 // 146 // The following are defines for the bit fields in the 147 // DTHE_O_AES_IMIS register. 148 // 149 //****************************************************************************** 150 #define DTHE_AES_IMIS_DOUT 0x00000008 // Output Data movement is done 151 #define DTHE_AES_IMIS_DIN 0x00000004 // input Data movement is done 152 #define DTHE_AES_IMIS_COUT 0x00000002 // Context output is done 153 #define DTHE_AES_IMIS_CIN 0x00000001 // context input is done 154 //****************************************************************************** 155 // 156 // The following are defines for the bit fields in the 157 // DTHE_O_AES_ICIS register. 158 // 159 //****************************************************************************** 160 #define DTHE_AES_ICIS_DOUT 0x00000008 // Clear “output Data movement 161 // done” flag 162 #define DTHE_AES_ICIS_DIN 0x00000004 // Clear “input Data movement done” 163 // flag 164 #define DTHE_AES_ICIS_COUT 0x00000002 // Clear “Context output done” flag 165 #define DTHE_AES_ICIS_CIN 0x00000001 // Clear “context input done” flag 166 //****************************************************************************** 167 // 168 // The following are defines for the bit fields in the 169 // DTHE_O_DES_IMST register. 170 // 171 //****************************************************************************** 172 #define DTHE_DES_IMST_DOUT 0x00000008 // Data out: this interrupt is 173 // raised when DMA finishes writing 174 // last word of the process result 175 #define DTHE_DES_IMST_DIN 0x00000004 // Data in: this interrupt is 176 // raised when DMA writes last word 177 // of input data to internal FIFO of 178 // the engine 179 #define DTHE_DES_IMST_CIN 0x00000001 // context in: this interrupt is 180 // raised when DMA complets Context 181 // write to internal register 182 //****************************************************************************** 183 // 184 // The following are defines for the bit fields in the 185 // DTHE_O_DES_IRIS register. 186 // 187 //****************************************************************************** 188 #define DTHE_DES_IRIS_DOUT 0x00000008 // Output Data movement is done 189 #define DTHE_DES_IRIS_DIN 0x00000004 // input Data movement is done 190 #define DTHE_DES_IRIS_CIN 0x00000001 // context input is done 191 //****************************************************************************** 192 // 193 // The following are defines for the bit fields in the 194 // DTHE_O_DES_IMIS register. 195 // 196 //****************************************************************************** 197 #define DTHE_DES_IMIS_DOUT 0x00000008 // Output Data movement is done 198 #define DTHE_DES_IMIS_DIN 0x00000004 // input Data movement is done 199 #define DTHE_DES_IMIS_CIN 0x00000001 // context input is done 200 //****************************************************************************** 201 // 202 // The following are defines for the bit fields in the 203 // DTHE_O_DES_ICIS register. 204 // 205 //****************************************************************************** 206 #define DTHE_DES_ICIS_DOUT 0x00000008 // Clear “output Data movement 207 // done” flag 208 #define DTHE_DES_ICIS_DIN 0x00000004 // Clear “input Data movement done” 209 // flag 210 #define DTHE_DES_ICIS_CIN 0x00000001 // Clear "context input done” flag 211 //****************************************************************************** 212 // 213 // The following are defines for the bit fields in the 214 // DTHE_O_EIP_CGCFG register. 215 // 216 //****************************************************************************** 217 #define DTHE_EIP_CGCFG_EIP29_CFG \ 218 0x00000010 // Clock gating protocol setting 219 // for EIP29T. 0 – Follow direct 220 // protocol 1 – Follow idle_req/ack 221 // protocol. 222 223 #define DTHE_EIP_CGCFG_EIP75_CFG \ 224 0x00000008 // Clock gating protocol setting 225 // for EIP75T. 0 – Follow direct 226 // protocol 1 – Follow idle_req/ack 227 // protocol. 228 229 #define DTHE_EIP_CGCFG_EIP16_CFG \ 230 0x00000004 // Clock gating protocol setting 231 // for DES. 0 – Follow direct 232 // protocol 1 – Follow idle_req/ack 233 // protocol. 234 235 #define DTHE_EIP_CGCFG_EIP36_CFG \ 236 0x00000002 // Clock gating protocol setting 237 // for AES. 0 – Follow direct 238 // protocol 1 – Follow idle_req/ack 239 // protocol. 240 241 #define DTHE_EIP_CGCFG_EIP57_CFG \ 242 0x00000001 // Clock gating protocol setting 243 // for SHAMD5. 0 – Follow direct 244 // protocol 1 – Follow idle_req/ack 245 // protocol. 246 247 //****************************************************************************** 248 // 249 // The following are defines for the bit fields in the 250 // DTHE_O_EIP_CGREQ register. 251 // 252 //****************************************************************************** 253 #define DTHE_EIP_CGREQ_Key_M 0xF0000000 // When “0x5” write “1” to lower 254 // bits [4:0] will set the bit. 255 // Write “0” will be ignored When 256 // “0x2” write “1” to lower bit 257 // [4:0] will clear the bit. Write 258 // “0” will be ignored for other key 259 // value, regular read write 260 // operation 261 #define DTHE_EIP_CGREQ_Key_S 28 262 #define DTHE_EIP_CGREQ_EIP29_REQ \ 263 0x00000010 // 0 – request clock gating 1 – 264 // request to un-gate the clock. 265 266 #define DTHE_EIP_CGREQ_EIP75_REQ \ 267 0x00000008 // 0 – request clock gating 1 – 268 // request to un-gate the clock. 269 270 #define DTHE_EIP_CGREQ_EIP16_REQ \ 271 0x00000004 // 0 – request clock gating 1 – 272 // request to un-gate the clock. 273 274 #define DTHE_EIP_CGREQ_EIP36_REQ \ 275 0x00000002 // 0 – request clock gating 1 – 276 // request to un-gate the clock. 277 278 #define DTHE_EIP_CGREQ_EIP57_REQ \ 279 0x00000001 // 0 – request clock gating 1 – 280 // request to un-gate the clock. 281 282 //****************************************************************************** 283 // 284 // The following are defines for the bit fields in the DTHE_O_CRC_CTRL register. 285 // 286 //****************************************************************************** 287 #define DTHE_CRC_CTRL_INIT_M 0x00006000 // Initialize the CRC 00 – use SEED 288 // register context as starting 289 // value 10 – all “zero” 11 – all 290 // “one” This is self clearing. With 291 // first write to data register this 292 // value clears to zero and remain 293 // zero for rest of the operation 294 // unless written again 295 #define DTHE_CRC_CTRL_INIT_S 13 296 #define DTHE_CRC_CTRL_SIZE 0x00001000 // Input data size 0 – 32 bit 1 – 8 297 // bit 298 #define DTHE_CRC_CTRL_OINV 0x00000200 // Inverse the bits of result 299 // before storing to CRC_RSLT_PP0 300 #define DTHE_CRC_CTRL_OBR 0x00000100 // Bit reverse the output result 301 // byte before storing to 302 // CRC_RSLT_PP0. applicable for all 303 // bytes in word 304 #define DTHE_CRC_CTRL_IBR 0x00000080 // Bit reverse the input byte. For 305 // all bytes in word 306 #define DTHE_CRC_CTRL_ENDIAN_M \ 307 0x00000030 // Endian control [0] – swap byte 308 // in half-word [1] – swap half word 309 310 #define DTHE_CRC_CTRL_ENDIAN_S 4 311 #define DTHE_CRC_CTRL_TYPE_M 0x0000000F // Type of operation 0000 – 312 // polynomial 0x8005 0001 – 313 // polynomial 0x1021 0010 – 314 // polynomial 0x4C11DB7 0011 – 315 // polynomial 0x1EDC6F41 1000 – TCP 316 // checksum TYPE in DTHE_S_CRC_CTRL 317 // & DTHE_S_CRC_CTRL should be 318 // exclusive 319 #define DTHE_CRC_CTRL_TYPE_S 0 320 //****************************************************************************** 321 // 322 // The following are defines for the bit fields in the DTHE_O_CRC_SEED register. 323 // 324 //****************************************************************************** 325 #define DTHE_CRC_SEED_SEED_M 0xFFFFFFFF // Starting seed of CRC and 326 // checksum operation. Please see 327 // CTRL register for more detail. 328 // This resister also holds the 329 // latest result of CRC or checksum 330 // operation 331 #define DTHE_CRC_SEED_SEED_S 0 332 //****************************************************************************** 333 // 334 // The following are defines for the bit fields in the DTHE_O_CRC_DIN register. 335 // 336 //****************************************************************************** 337 #define DTHE_CRC_DIN_DATA_IN_M \ 338 0xFFFFFFFF // Input data for CRC or checksum 339 // operation 340 341 #define DTHE_CRC_DIN_DATA_IN_S 0 342 //****************************************************************************** 343 // 344 // The following are defines for the bit fields in the 345 // DTHE_O_CRC_RSLT_PP register. 346 // 347 //****************************************************************************** 348 #define DTHE_CRC_RSLT_PP_RSLT_PP_M \ 349 0xFFFFFFFF // Input data for CRC or checksum 350 // operation 351 352 #define DTHE_CRC_RSLT_PP_RSLT_PP_S 0 353 //****************************************************************************** 354 // 355 // The following are defines for the bit fields in the 356 // DTHE_O_RAND_KEY0 register. 357 // 358 //****************************************************************************** 359 #define DTHE_RAND_KEY0_KEY_M 0xFFFFFFFF // Device Specific Randon key 360 // [31:0] 361 #define DTHE_RAND_KEY0_KEY_S 0 362 //****************************************************************************** 363 // 364 // The following are defines for the bit fields in the 365 // DTHE_O_RAND_KEY1 register. 366 // 367 //****************************************************************************** 368 #define DTHE_RAND_KEY1_KEY_M 0xFFFFFFFF // Device Specific Randon key 369 // [63:32] 370 #define DTHE_RAND_KEY1_KEY_S 0 371 //****************************************************************************** 372 // 373 // The following are defines for the bit fields in the 374 // DTHE_O_RAND_KEY2 register. 375 // 376 //****************************************************************************** 377 #define DTHE_RAND_KEY2_KEY_M 0xFFFFFFFF // Device Specific Randon key 378 // [95:34] 379 #define DTHE_RAND_KEY2_KEY_S 0 380 //****************************************************************************** 381 // 382 // The following are defines for the bit fields in the 383 // DTHE_O_RAND_KEY3 register. 384 // 385 //****************************************************************************** 386 #define DTHE_RAND_KEY3_KEY_M 0xFFFFFFFF // Device Specific Randon key 387 // [127:96] 388 #define DTHE_RAND_KEY3_KEY_S 0 389 390 391 392 #endif // __HW_DTHE_H__ 393