/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AArch64/ |
H A D | framelayout-sve.mir | 504 …W_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… 505 …_CFA_expression: reg73 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_… 506 …_CFA_expression: reg74 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_… 575 …W_CFA_expression: reg72 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… 576 …_CFA_expression: reg73 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_… 577 …_CFA_expression: reg74 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_… 578 …_CFA_expression: reg75 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -32, DW_OP_bregx 0x2e +0, DW_OP_… 579 …_CFA_expression: reg76 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -40, DW_OP_bregx 0x2e +0, DW_OP_… 580 …_CFA_expression: reg77 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -48, DW_OP_bregx 0x2e +0, DW_OP_… 669 …W_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… [all …]
|
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | debug-info-sve-dbg-value.mir | 15 # CHECK2: : DW_OP_breg31 WSP+16, DW_OP_lit16, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 18 # CHECK3: : DW_OP_breg31 WSP+16, DW_OP_lit8, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 21 # CHECK4: : DW_OP_breg31 WSP+16, DW_OP_lit7, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 24 # CHECK5: : DW_OP_breg31 WSP+16, DW_OP_lit6, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 67 …!20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 2, DW_OP_bregx, 46, 0, DW… 73 …!26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 1, DW_OP_bregx, 46, 0, DW…
|
H A D | framelayout-sve.mir | 505 …W_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… 506 …_CFA_expression: reg73 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_… 507 …_CFA_expression: reg74 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_… 576 …W_CFA_expression: reg72 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… 577 …_CFA_expression: reg73 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_… 578 …_CFA_expression: reg74 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_… 579 …_CFA_expression: reg75 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -32, DW_OP_bregx 0x2e +0, DW_OP_… 580 …_CFA_expression: reg76 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -40, DW_OP_bregx 0x2e +0, DW_OP_… 581 …_CFA_expression: reg77 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -48, DW_OP_bregx 0x2e +0, DW_OP_… 670 …W_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… [all …]
|
H A D | debug-info-sve-dbg-declare.mir | 11 # CHECKZ0: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit8, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_… 13 # CHECKZ1: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit16, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 15 # CHECKP0: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit17, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 17 # CHECKP1: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit18, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 19 # CHECKLV0: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x20, DW_OP_bregx VG+0, DW_OP_mul,… 21 # CHECKLV1: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x28, DW_OP_bregx VG+0, DW_OP_mul,… 23 # CHECKLP0: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x29, DW_OP_bregx VG+0, DW_OP_mul,… 25 # CHECKLP1: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x2a, DW_OP_bregx VG+0, DW_OP_mul,… 106 …!20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 2, DW_OP_bregx, 46, 0, DW… 112 …!26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 1, DW_OP_bregx, 46, 0, DW…
|
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | debug-info-sve-dbg-value.mir | 15 # CHECK2: : DW_OP_breg31 WSP+16, DW_OP_lit16, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 18 # CHECK3: : DW_OP_breg31 WSP+16, DW_OP_lit8, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 21 # CHECK4: : DW_OP_breg31 WSP+16, DW_OP_lit7, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 24 # CHECK5: : DW_OP_breg31 WSP+16, DW_OP_lit6, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 67 …!20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 2, DW_OP_bregx, 46, 0, DW… 73 …!26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 1, DW_OP_bregx, 46, 0, DW…
|
H A D | framelayout-sve.mir | 505 …W_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… 506 …_CFA_expression: reg73 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_… 507 …_CFA_expression: reg74 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_… 576 …W_CFA_expression: reg72 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… 577 …_CFA_expression: reg73 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_… 578 …_CFA_expression: reg74 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_… 579 …_CFA_expression: reg75 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -32, DW_OP_bregx 0x2e +0, DW_OP_… 580 …_CFA_expression: reg76 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -40, DW_OP_bregx 0x2e +0, DW_OP_… 581 …_CFA_expression: reg77 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -48, DW_OP_bregx 0x2e +0, DW_OP_… 670 …W_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… [all …]
|
H A D | debug-info-sve-dbg-declare.mir | 11 # CHECKZ0: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit8, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_… 13 # CHECKZ1: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit16, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 15 # CHECKP0: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit17, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 17 # CHECKP1: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit18, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 19 # CHECKLV0: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x20, DW_OP_bregx VG+0, DW_OP_mul,… 21 # CHECKLV1: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x28, DW_OP_bregx VG+0, DW_OP_mul,… 23 # CHECKLP0: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x29, DW_OP_bregx VG+0, DW_OP_mul,… 25 # CHECKLP1: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x2a, DW_OP_bregx VG+0, DW_OP_mul,… 106 …!20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 2, DW_OP_bregx, 46, 0, DW… 112 …!26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 1, DW_OP_bregx, 46, 0, DW…
|
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/AArch64/ |
H A D | debug-info-sve-dbg-value.mir | 15 # CHECK2: : DW_OP_breg31 WSP+16, DW_OP_lit16, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 18 # CHECK3: : DW_OP_breg31 WSP+16, DW_OP_lit8, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 21 # CHECK4: : DW_OP_breg31 WSP+16, DW_OP_lit7, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 24 # CHECK5: : DW_OP_breg31 WSP+16, DW_OP_lit6, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 67 …!20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 2, DW_OP_bregx, 46, 0, DW… 73 …!26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 1, DW_OP_bregx, 46, 0, DW…
|
H A D | framelayout-sve.mir | 505 …W_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… 506 …_CFA_expression: reg73 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_… 507 …_CFA_expression: reg74 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_… 576 …W_CFA_expression: reg72 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… 577 …_CFA_expression: reg73 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_… 578 …_CFA_expression: reg74 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_… 579 …_CFA_expression: reg75 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -32, DW_OP_bregx 0x2e +0, DW_OP_… 580 …_CFA_expression: reg76 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -40, DW_OP_bregx 0x2e +0, DW_OP_… 581 …_CFA_expression: reg77 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -48, DW_OP_bregx 0x2e +0, DW_OP_… 670 …W_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… [all …]
|
H A D | debug-info-sve-dbg-declare.mir | 11 # CHECKZ0: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit8, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_… 13 # CHECKZ1: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit16, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 15 # CHECKP0: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit17, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 17 # CHECKP1: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit18, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 19 # CHECKLV0: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x20, DW_OP_bregx VG+0, DW_OP_mul,… 21 # CHECKLV1: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x28, DW_OP_bregx VG+0, DW_OP_mul,… 23 # CHECKLP0: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x29, DW_OP_bregx VG+0, DW_OP_mul,… 25 # CHECKLP1: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x2a, DW_OP_bregx VG+0, DW_OP_mul,… 106 …!20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 2, DW_OP_bregx, 46, 0, DW… 112 …!26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 1, DW_OP_bregx, 46, 0, DW…
|
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AArch64/ |
H A D | debug-info-sve-dbg-value.mir | 15 # CHECK2: : DW_OP_breg31 WSP+16, DW_OP_lit16, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 18 # CHECK3: : DW_OP_breg31 WSP+16, DW_OP_lit8, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 21 # CHECK4: : DW_OP_breg31 WSP+16, DW_OP_lit7, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 24 # CHECK5: : DW_OP_breg31 WSP+16, DW_OP_lit6, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 67 …!20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 2, DW_OP_bregx, 46, 0, DW… 73 …!26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 1, DW_OP_bregx, 46, 0, DW…
|
H A D | framelayout-sve.mir | 505 …W_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… 506 …_CFA_expression: reg73 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_… 507 …_CFA_expression: reg74 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_… 576 …W_CFA_expression: reg72 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… 577 …_CFA_expression: reg73 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_… 578 …_CFA_expression: reg74 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_… 579 …_CFA_expression: reg75 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -32, DW_OP_bregx 0x2e +0, DW_OP_… 580 …_CFA_expression: reg76 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -40, DW_OP_bregx 0x2e +0, DW_OP_… 581 …_CFA_expression: reg77 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -48, DW_OP_bregx 0x2e +0, DW_OP_… 670 …W_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… [all …]
|
H A D | debug-info-sve-dbg-declare.mir | 11 # CHECKZ0: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit8, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_… 13 # CHECKZ1: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit16, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 15 # CHECKP0: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit17, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 17 # CHECKP1: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit18, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 19 # CHECKLV0: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x20, DW_OP_bregx VG+0, DW_OP_mul,… 21 # CHECKLV1: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x28, DW_OP_bregx VG+0, DW_OP_mul,… 23 # CHECKLP0: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x29, DW_OP_bregx VG+0, DW_OP_mul,… 25 # CHECKLP1: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x2a, DW_OP_bregx VG+0, DW_OP_mul,… 106 …!20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 2, DW_OP_bregx, 46, 0, DW… 112 …!26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 1, DW_OP_bregx, 46, 0, DW…
|
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | debug-info-sve-dbg-value.mir | 15 # CHECK2: : DW_OP_breg31 WSP+16, DW_OP_lit16, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 18 # CHECK3: : DW_OP_breg31 WSP+16, DW_OP_lit8, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 21 # CHECK4: : DW_OP_breg31 WSP+16, DW_OP_lit7, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 24 # CHECK5: : DW_OP_breg31 WSP+16, DW_OP_lit6, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 67 …!20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 2, DW_OP_bregx, 46, 0, DW… 73 …!26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 1, DW_OP_bregx, 46, 0, DW…
|
H A D | framelayout-sve.mir | 505 …W_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… 506 …_CFA_expression: reg73 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_… 507 …_CFA_expression: reg74 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_… 576 …W_CFA_expression: reg72 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… 577 …_CFA_expression: reg73 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_… 578 …_CFA_expression: reg74 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_… 579 …_CFA_expression: reg75 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -32, DW_OP_bregx 0x2e +0, DW_OP_… 580 …_CFA_expression: reg76 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -40, DW_OP_bregx 0x2e +0, DW_OP_… 581 …_CFA_expression: reg77 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -48, DW_OP_bregx 0x2e +0, DW_OP_… 670 …W_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… [all …]
|
H A D | debug-info-sve-dbg-declare.mir | 11 # CHECKZ0: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit8, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_… 13 # CHECKZ1: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit16, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 15 # CHECKP0: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit17, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 17 # CHECKP1: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit18, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 19 # CHECKLV0: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x20, DW_OP_bregx VG+0, DW_OP_mul,… 21 # CHECKLV1: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x28, DW_OP_bregx VG+0, DW_OP_mul,… 23 # CHECKLP0: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x29, DW_OP_bregx VG+0, DW_OP_mul,… 25 # CHECKLP1: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x2a, DW_OP_bregx VG+0, DW_OP_mul,… 106 …!20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 2, DW_OP_bregx, 46, 0, DW… 112 …!26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 1, DW_OP_bregx, 46, 0, DW…
|
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | debug-info-sve-dbg-value.mir | 15 # CHECK2: : DW_OP_breg31 WSP+16, DW_OP_lit16, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 18 # CHECK3: : DW_OP_breg31 WSP+16, DW_OP_lit8, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 21 # CHECK4: : DW_OP_breg31 WSP+16, DW_OP_lit7, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 24 # CHECK5: : DW_OP_breg31 WSP+16, DW_OP_lit6, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 67 …!20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 2, DW_OP_bregx, 46, 0, DW… 73 …!26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 1, DW_OP_bregx, 46, 0, DW…
|
H A D | framelayout-sve.mir | 505 …W_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… 506 …_CFA_expression: reg73 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_… 507 …_CFA_expression: reg74 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_… 576 …W_CFA_expression: reg72 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… 577 …_CFA_expression: reg73 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_… 578 …_CFA_expression: reg74 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_… 579 …_CFA_expression: reg75 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -32, DW_OP_bregx 0x2e +0, DW_OP_… 580 …_CFA_expression: reg76 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -40, DW_OP_bregx 0x2e +0, DW_OP_… 581 …_CFA_expression: reg77 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -48, DW_OP_bregx 0x2e +0, DW_OP_… 670 …W_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… [all …]
|
H A D | debug-info-sve-dbg-declare.mir | 11 # CHECKZ0: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit8, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_… 13 # CHECKZ1: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit16, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 15 # CHECKP0: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit17, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 17 # CHECKP1: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit18, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 19 # CHECKLV0: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x20, DW_OP_bregx VG+0, DW_OP_mul,… 21 # CHECKLV1: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x28, DW_OP_bregx VG+0, DW_OP_mul,… 23 # CHECKLP0: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x29, DW_OP_bregx VG+0, DW_OP_mul,… 25 # CHECKLP1: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x2a, DW_OP_bregx VG+0, DW_OP_mul,… 106 …!20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 2, DW_OP_bregx, 46, 0, DW… 112 …!26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 1, DW_OP_bregx, 46, 0, DW…
|
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | debug-info-sve-dbg-value.mir | 15 # CHECK2: : DW_OP_breg31 WSP+16, DW_OP_lit16, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 18 # CHECK3: : DW_OP_breg31 WSP+16, DW_OP_lit8, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 21 # CHECK4: : DW_OP_breg31 WSP+16, DW_OP_lit7, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 24 # CHECK5: : DW_OP_breg31 WSP+16, DW_OP_lit6, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 67 …!20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 2, DW_OP_bregx, 46, 0, DW… 73 …!26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 1, DW_OP_bregx, 46, 0, DW…
|
H A D | framelayout-sve.mir | 505 …W_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… 506 …_CFA_expression: reg73 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_… 507 …_CFA_expression: reg74 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_… 576 …W_CFA_expression: reg72 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… 577 …_CFA_expression: reg73 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_… 578 …_CFA_expression: reg74 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_… 579 …_CFA_expression: reg75 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -32, DW_OP_bregx 0x2e +0, DW_OP_… 580 …_CFA_expression: reg76 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -40, DW_OP_bregx 0x2e +0, DW_OP_… 581 …_CFA_expression: reg77 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -48, DW_OP_bregx 0x2e +0, DW_OP_… 670 …W_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… [all …]
|
H A D | debug-info-sve-dbg-declare.mir | 11 # CHECKZ0: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit8, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_… 13 # CHECKZ1: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit16, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 15 # CHECKP0: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit17, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 17 # CHECKP1: DW_AT_location (DW_OP_fbreg +0, DW_OP_lit18, DW_OP_bregx VG+0, DW_OP_mul, DW_OP… 19 # CHECKLV0: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x20, DW_OP_bregx VG+0, DW_OP_mul,… 21 # CHECKLV1: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x28, DW_OP_bregx VG+0, DW_OP_mul,… 23 # CHECKLP0: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x29, DW_OP_bregx VG+0, DW_OP_mul,… 25 # CHECKLP1: DW_AT_location (DW_OP_fbreg +0, DW_OP_constu 0x2a, DW_OP_bregx VG+0, DW_OP_mul,… 106 …!20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 2, DW_OP_bregx, 46, 0, DW… 112 …!26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 1, DW_OP_bregx, 46, 0, DW…
|
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AArch64/ |
H A D | debug-info-sve-dbg-value.mir | 15 # CHECK2: : DW_OP_breg31 WSP+16, DW_OP_lit16, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 18 # CHECK3: : DW_OP_breg31 WSP+16, DW_OP_lit8, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 21 # CHECK4: : DW_OP_breg31 WSP+16, DW_OP_lit7, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 24 # CHECK5: : DW_OP_breg31 WSP+16, DW_OP_lit6, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) 67 …!20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 2, DW_OP_bregx, 46, 0, DW… 73 …!26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 1, DW_OP_bregx, 46, 0, DW…
|
H A D | framelayout-sve.mir | 505 …W_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… 506 …_CFA_expression: reg73 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_… 507 …_CFA_expression: reg74 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_… 576 …W_CFA_expression: reg72 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… 577 …_CFA_expression: reg73 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_… 578 …_CFA_expression: reg74 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_… 579 …_CFA_expression: reg75 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -32, DW_OP_bregx 0x2e +0, DW_OP_… 580 …_CFA_expression: reg76 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -40, DW_OP_bregx 0x2e +0, DW_OP_… 581 …_CFA_expression: reg77 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -48, DW_OP_bregx 0x2e +0, DW_OP_… 670 …W_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… [all …]
|
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AArch64/ |
H A D | framelayout-sve.mir | 505 …W_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… 506 …_CFA_expression: reg73 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_… 507 …_CFA_expression: reg74 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_… 576 …W_CFA_expression: reg72 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… 577 …_CFA_expression: reg73 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_… 578 …_CFA_expression: reg74 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_… 579 …_CFA_expression: reg75 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -32, DW_OP_bregx 0x2e +0, DW_OP_… 580 …_CFA_expression: reg76 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -40, DW_OP_bregx 0x2e +0, DW_OP_… 581 …_CFA_expression: reg77 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -48, DW_OP_bregx 0x2e +0, DW_OP_… 670 …W_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_… [all …]
|