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Searched refs:DiffSeqs (Results 1 – 25 of 31) sorted by relevance

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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp892 SequenceToOffsetTable<DiffVec> DiffSeqs; in runMCDesc() local
920 DiffSeqs.add(SubRegLists[i]); in runMCDesc()
932 DiffSeqs.add(SuperRegLists[i]); in runMCDesc()
958 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); in runMCDesc()
974 DiffSeqs.layout(); in runMCDesc()
984 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
1020 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) in runMCDesc()
1022 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " in runMCDesc()
/dports/devel/llvm11/llvm-11.0.1.src/utils/TableGen/
H A DRegisterInfoEmitter.cpp892 SequenceToOffsetTable<DiffVec> DiffSeqs; in runMCDesc() local
920 DiffSeqs.add(SubRegLists[i]); in runMCDesc()
932 DiffSeqs.add(SuperRegLists[i]); in runMCDesc()
958 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); in runMCDesc()
974 DiffSeqs.layout(); in runMCDesc()
984 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
1020 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) in runMCDesc()
1022 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " in runMCDesc()
/dports/devel/llvm90/llvm-9.0.1.src/utils/TableGen/
H A DRegisterInfoEmitter.cpp878 SequenceToOffsetTable<DiffVec> DiffSeqs; in runMCDesc() local
906 DiffSeqs.add(SubRegLists[i]); in runMCDesc()
918 DiffSeqs.add(SuperRegLists[i]); in runMCDesc()
944 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); in runMCDesc()
960 DiffSeqs.layout(); in runMCDesc()
970 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
1007 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) in runMCDesc()
1009 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " in runMCDesc()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp889 SequenceToOffsetTable<DiffVec> DiffSeqs; in runMCDesc() local
917 DiffSeqs.add(SubRegLists[i]); in runMCDesc()
929 DiffSeqs.add(SuperRegLists[i]); in runMCDesc()
955 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); in runMCDesc()
971 DiffSeqs.layout(); in runMCDesc()
981 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
1017 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) in runMCDesc()
1019 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " in runMCDesc()
/dports/devel/llvm10/llvm-10.0.1.src/utils/TableGen/
H A DRegisterInfoEmitter.cpp878 SequenceToOffsetTable<DiffVec> DiffSeqs; in runMCDesc() local
906 DiffSeqs.add(SubRegLists[i]); in runMCDesc()
918 DiffSeqs.add(SuperRegLists[i]); in runMCDesc()
944 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); in runMCDesc()
960 DiffSeqs.layout(); in runMCDesc()
970 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
1007 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) in runMCDesc()
1009 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " in runMCDesc()
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp878 SequenceToOffsetTable<DiffVec> DiffSeqs; in runMCDesc() local
906 DiffSeqs.add(SubRegLists[i]); in runMCDesc()
918 DiffSeqs.add(SuperRegLists[i]); in runMCDesc()
944 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); in runMCDesc()
960 DiffSeqs.layout(); in runMCDesc()
970 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
1007 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) in runMCDesc()
1009 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " in runMCDesc()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp889 SequenceToOffsetTable<DiffVec> DiffSeqs; in runMCDesc() local
917 DiffSeqs.add(SubRegLists[i]); in runMCDesc()
929 DiffSeqs.add(SuperRegLists[i]); in runMCDesc()
955 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); in runMCDesc()
971 DiffSeqs.layout(); in runMCDesc()
981 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
1017 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) in runMCDesc()
1019 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " in runMCDesc()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp892 SequenceToOffsetTable<DiffVec> DiffSeqs; in runMCDesc() local
920 DiffSeqs.add(SubRegLists[i]); in runMCDesc()
932 DiffSeqs.add(SuperRegLists[i]); in runMCDesc()
958 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); in runMCDesc()
974 DiffSeqs.layout(); in runMCDesc()
984 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
1020 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) in runMCDesc()
1022 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " in runMCDesc()
/dports/devel/llvm80/llvm-8.0.1.src/utils/TableGen/
H A DRegisterInfoEmitter.cpp879 SequenceToOffsetTable<DiffVec> DiffSeqs; in runMCDesc() local
907 DiffSeqs.add(SubRegLists[i]); in runMCDesc()
919 DiffSeqs.add(SuperRegLists[i]); in runMCDesc()
945 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); in runMCDesc()
961 DiffSeqs.layout(); in runMCDesc()
971 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
1008 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) in runMCDesc()
1010 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " in runMCDesc()
/dports/devel/llvm70/llvm-7.0.1.src/utils/TableGen/
H A DRegisterInfoEmitter.cpp839 SequenceToOffsetTable<DiffVec> DiffSeqs; in runMCDesc() local
867 DiffSeqs.add(SubRegLists[i]); in runMCDesc()
879 DiffSeqs.add(SuperRegLists[i]); in runMCDesc()
905 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); in runMCDesc()
921 DiffSeqs.layout(); in runMCDesc()
931 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
968 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) in runMCDesc()
970 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " in runMCDesc()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp882 SequenceToOffsetTable<DiffVec> DiffSeqs; in runMCDesc() local
910 DiffSeqs.add(SubRegLists[i]); in runMCDesc()
922 DiffSeqs.add(SuperRegLists[i]); in runMCDesc()
948 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); in runMCDesc()
964 DiffSeqs.layout(); in runMCDesc()
974 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
1010 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) in runMCDesc()
1012 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " in runMCDesc()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp882 SequenceToOffsetTable<DiffVec> DiffSeqs; in runMCDesc() local
910 DiffSeqs.add(SubRegLists[i]); in runMCDesc()
922 DiffSeqs.add(SuperRegLists[i]); in runMCDesc()
948 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); in runMCDesc()
964 DiffSeqs.layout(); in runMCDesc()
974 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
1010 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) in runMCDesc()
1012 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " in runMCDesc()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp882 SequenceToOffsetTable<DiffVec> DiffSeqs; in runMCDesc() local
910 DiffSeqs.add(SubRegLists[i]); in runMCDesc()
922 DiffSeqs.add(SuperRegLists[i]); in runMCDesc()
948 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); in runMCDesc()
964 DiffSeqs.layout(); in runMCDesc()
974 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
1010 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) in runMCDesc()
1012 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " in runMCDesc()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp882 SequenceToOffsetTable<DiffVec> DiffSeqs; in runMCDesc() local
910 DiffSeqs.add(SubRegLists[i]); in runMCDesc()
922 DiffSeqs.add(SuperRegLists[i]); in runMCDesc()
948 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); in runMCDesc()
964 DiffSeqs.layout(); in runMCDesc()
974 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
1010 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) in runMCDesc()
1012 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " in runMCDesc()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/utils/TableGen/
H A DRegisterInfoEmitter.cpp882 SequenceToOffsetTable<DiffVec> DiffSeqs; in runMCDesc() local
910 DiffSeqs.add(SubRegLists[i]); in runMCDesc()
922 DiffSeqs.add(SuperRegLists[i]); in runMCDesc()
948 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); in runMCDesc()
964 DiffSeqs.layout(); in runMCDesc()
974 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
1010 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) in runMCDesc()
1012 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " in runMCDesc()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp882 SequenceToOffsetTable<DiffVec> DiffSeqs; in runMCDesc() local
910 DiffSeqs.add(SubRegLists[i]); in runMCDesc()
922 DiffSeqs.add(SuperRegLists[i]); in runMCDesc()
948 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); in runMCDesc()
964 DiffSeqs.layout(); in runMCDesc()
974 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
1010 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) in runMCDesc()
1012 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " in runMCDesc()
/dports/emulators/qemu/qemu-6.2.0/capstone/contrib/sysz_update/
H A D0001-capstone-generate-GenRegisterInfo.inc.patch147 DiffSeqs.emit(OS, printDiff16);
/dports/emulators/qemu60/qemu-6.0.0/capstone/contrib/sysz_update/
H A D0001-capstone-generate-GenRegisterInfo.inc.patch147 DiffSeqs.emit(OS, printDiff16);
/dports/emulators/qemu5/qemu-5.2.0/capstone/contrib/sysz_update/
H A D0001-capstone-generate-GenRegisterInfo.inc.patch147 DiffSeqs.emit(OS, printDiff16);
/dports/emulators/qemu/qemu-6.2.0/capstone/contrib/riscv_update/
H A D0001-capstone-riscv-patchs.patch185 + DiffSeqs.emit(OS, printDiff16);
2849 DiffSeqs.emit(OS, printDiff16);
H A D0003-clear-old-patchs.patch175 - DiffSeqs.emit(OS, printDiff16);
/dports/emulators/qemu60/qemu-6.0.0/capstone/contrib/riscv_update/
H A D0001-capstone-riscv-patchs.patch185 + DiffSeqs.emit(OS, printDiff16);
2849 DiffSeqs.emit(OS, printDiff16);
H A D0003-clear-old-patchs.patch175 - DiffSeqs.emit(OS, printDiff16);
/dports/emulators/qemu5/qemu-5.2.0/capstone/contrib/riscv_update/
H A D0001-capstone-riscv-patchs.patch185 + DiffSeqs.emit(OS, printDiff16);
2849 DiffSeqs.emit(OS, printDiff16);
H A D0003-clear-old-patchs.patch175 - DiffSeqs.emit(OS, printDiff16);

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