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Searched refs:DstReg64 (Results 1 – 17 of 17) sorted by relevance

/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp2721 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, in LowerF64Op() local
2723 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2724 DstReg64, Hi32); in LowerF64Op()
2725 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2726 DstReg64, Lo32); in LowerF64Op()
2727 return DstReg64; in LowerF64Op()
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp2715 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, in LowerF64Op() local
2717 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2718 DstReg64, Hi32); in LowerF64Op()
2719 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2720 DstReg64, Lo32); in LowerF64Op()
2721 return DstReg64; in LowerF64Op()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp2721 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, in LowerF64Op() local
2723 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2724 DstReg64, Hi32); in LowerF64Op()
2725 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2726 DstReg64, Lo32); in LowerF64Op()
2727 return DstReg64; in LowerF64Op()
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/Sparc/
H A DSparcISelLowering.cpp2715 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, in LowerF64Op() local
2717 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2718 DstReg64, Hi32); in LowerF64Op()
2719 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2720 DstReg64, Lo32); in LowerF64Op()
2721 return DstReg64; in LowerF64Op()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp2726 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, in LowerF64Op() local
2728 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2729 DstReg64, Hi32); in LowerF64Op()
2730 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2731 DstReg64, Lo32); in LowerF64Op()
2732 return DstReg64; in LowerF64Op()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Sparc/
H A DSparcISelLowering.cpp2726 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, in LowerF64Op() local
2728 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2729 DstReg64, Hi32); in LowerF64Op()
2730 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2731 DstReg64, Lo32); in LowerF64Op()
2732 return DstReg64; in LowerF64Op()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp2723 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, in LowerF64Op() local
2725 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2726 DstReg64, Hi32); in LowerF64Op()
2727 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2728 DstReg64, Lo32); in LowerF64Op()
2729 return DstReg64; in LowerF64Op()
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/Sparc/
H A DSparcISelLowering.cpp2721 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, in LowerF64Op() local
2723 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2724 DstReg64, Hi32); in LowerF64Op()
2725 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2726 DstReg64, Lo32); in LowerF64Op()
2727 return DstReg64; in LowerF64Op()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp2726 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, in LowerF64Op() local
2728 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2729 DstReg64, Hi32); in LowerF64Op()
2730 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2731 DstReg64, Lo32); in LowerF64Op()
2732 return DstReg64; in LowerF64Op()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp2715 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, in LowerF64Op() local
2717 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2718 DstReg64, Hi32); in LowerF64Op()
2719 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2720 DstReg64, Lo32); in LowerF64Op()
2721 return DstReg64; in LowerF64Op()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp2726 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, in LowerF64Op() local
2728 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2729 DstReg64, Hi32); in LowerF64Op()
2730 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2731 DstReg64, Lo32); in LowerF64Op()
2732 return DstReg64; in LowerF64Op()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp2726 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, in LowerF64Op() local
2728 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2729 DstReg64, Hi32); in LowerF64Op()
2730 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2731 DstReg64, Lo32); in LowerF64Op()
2732 return DstReg64; in LowerF64Op()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp2723 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, in LowerF64Op() local
2725 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2726 DstReg64, Hi32); in LowerF64Op()
2727 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2728 DstReg64, Lo32); in LowerF64Op()
2729 return DstReg64; in LowerF64Op()
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/Sparc/
H A DSparcISelLowering.cpp2715 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, in LowerF64Op() local
2717 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2718 DstReg64, Hi32); in LowerF64Op()
2719 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2720 DstReg64, Lo32); in LowerF64Op()
2721 return DstReg64; in LowerF64Op()
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/Sparc/
H A DSparcISelLowering.cpp2715 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, in LowerF64Op() local
2717 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2718 DstReg64, Hi32); in LowerF64Op()
2719 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2720 DstReg64, Lo32); in LowerF64Op()
2721 return DstReg64; in LowerF64Op()
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/Sparc/
H A DSparcISelLowering.cpp2774 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, in LowerF64Op() local
2776 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2777 DstReg64, Hi32); in LowerF64Op()
2778 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2779 DstReg64, Lo32); in LowerF64Op()
2780 return DstReg64; in LowerF64Op()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp2726 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, in LowerF64Op() local
2728 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2729 DstReg64, Hi32); in LowerF64Op()
2730 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2731 DstReg64, Lo32); in LowerF64Op()
2732 return DstReg64; in LowerF64Op()