| /dports/devel/asl/asl-current/include/avr/ |
| H A D | eem2.inc | 23 EECR port 0x1f ; EEPROM Control Register
24 EERE avrbit EECR,0 ; Read Enable
25 EEPE avrbit EECR,1 ; Program Enable
26 EEMPE avrbit EECR,2 ; EEPROM Master Program Enable
27 EERIE avrbit EECR,3 ; Enable Ready Interrupt
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| H A D | ee90.inc | 26 EECR port 0x1c ; EEPROM Control Register
27 EERE avrbit EECR,0 ; Read Enable
28 EEWE avrbit EECR,1 ; Write Enable
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| H A D | regtn112.inc | 36 EECR port 0x1c ; EEPROM Control Register
37 EERE avrbit EECR,0 ; EEPROM Read Enable
38 EEWE avrbit EECR,1 ; EEPROM Write Enable
39 EEMWE avrbit EECR,2 ; EEPROM Multiple Write Enable
40 EERIE avrbit EECR,3 ; EEPROM Ready Interrupt Enable
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| H A D | regtn13.inc | 55 EECR port 0x1c ; EEPROM Control Register
56 EEPM1 avrbit EECR,5 ; EEPROM Programming Mode
57 EEPM0 avrbit EECR,4
58 EERIE avrbit EECR,3 ; EEPROM Ready Interrupt Enable
59 EEMPE avrbit EECR,2 ; EEPROM Master Program Enable
60 EEPE avrbit EECR,1 ; EEPROM Program Enable
61 EERE avrbit EECR,0 ; EEPROM Read Enable
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| H A D | eem.inc | 16 EEMWE avrbit EECR,2 ; EEPROM Master Write Enable
17 EERIE avrbit EECR,3 ; Enable Ready Interrupt
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| H A D | regtn15.inc | 44 EECR port 0x1c ; EEPROM Control Register
45 EERE avrbit EECR,0 ; EEPROM Read Enable
46 EEWE avrbit EECR,1 ; EEPROM Write Enable
47 EEMWE avrbit EECR,2 ; EEPROM Multiple Write Enable
48 EERIE avrbit EECR,3 ; EEPROM Ready Interrupt Enable
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| H A D | regtn43u.inc | 61 EECR port 0x1c ; EEPROM Control Register
62 EEPM1 avrbit EECR,5 ; EEPROM Program Mode
63 EEPM0 avrbit EECR,4
64 EERIE avrbit EECR,3 ; EEPROM Ready Interrupt Enable
65 EEMPE avrbit EECR,2 ; EEPROM Master Write Enable
66 EEPE avrbit EECR,1 ; EEPROM Write Enable
67 EERE avrbit EECR,0 ; EEPROM Read Enable
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| H A D | regtnx8.inc | 53 EECR port 0x1f ; EEPROM Control Register
54 EEPM1 avrbit EECR,5 ; EEPROM Program Mode
55 EEPM0 avrbit EECR,4
56 EERIE avrbit EECR,3 ; EEPROM Ready Interrupt Enable
57 EEMPE avrbit EECR,2 ; EEPROM Master Write Enable
58 EEPE avrbit EECR,1 ; EEPROM Write Enable
59 EERE avrbit EECR,0 ; EEPROM Read Enable
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| H A D | regtn26.inc | 48 EECR port 0x1c ; EEPROM Control Register
49 EERIE avrbit EECR,3 ; EEPROM Ready Interrupt Enable
50 EEMWE avrbit EECR,2 ; EEPROM Master Write Enable
51 EEWE avrbit EECR,1 ; EEPROM Write Enable
52 EERE avrbit EECR,0 ; EEPROM Read Enable
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| H A D | regtnx4.inc | 51 EECR port 0x1c ; EEPROM Control Register
52 EEPM1 avrbit EECR,5 ; EEPROM Program Mode
53 EEPM0 avrbit EECR,4
54 EERIE avrbit EECR,3 ; EEPROM Ready Interrupt Enable
55 EEMPE avrbit EECR,2 ; EEPROM Master Write Enable
56 EEPE avrbit EECR,1 ; EEPROM Write Enable
57 EERE avrbit EECR,0 ; EEPROM Read Enable
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| H A D | regtx313.inc | 54 EECR port 0x1c ; EEPROM Control Register
55 EEPM1 avrbit EECR,5 ; EEPROM Program Mode
56 EEPM0 avrbit EECR,4
57 EERIE avrbit EECR,3 ; EEPROM Ready Interrupt Enable
58 EEMPE avrbit EECR,2 ; EEPROM Master Write Enable
59 EEPE avrbit EECR,1 ; EEPROM Write Enable
60 EERE avrbit EECR,0 ; EEPROM Read Enable
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| H A D | regtnx61.inc | 59 EECR port 0x1c ; EEPROM Control Register
60 EEPM1 avrbit EECR,5 ; EEPROM Program Mode
61 EEPM0 avrbit EECR,4
62 EERIE avrbit EECR,3 ; EEPROM Ready Interrupt Enable
63 EEMPE avrbit EECR,2 ; EEPROM Master Write Enable
64 EEPE avrbit EECR,1 ; EEPROM Write Enable
65 EERE avrbit EECR,0 ; EEPROM Read Enable
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| H A D | regtnx7.inc | 72 EECR port 0x1f ; EEPROM Control Register
73 EEPM1 avrbit EECR,5 ; EEPROM Program Mode
74 EEPM0 avrbit EECR,4
75 EERIE avrbit EECR,3 ; EEPROM Ready Interrupt Enable
76 EEMPE avrbit EECR,2 ; EEPROM Master Write Enable
77 EEPE avrbit EECR,1 ; EEPROM Write Enable
78 EERE avrbit EECR,0 ; EEPROM Read Enable
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| H A D | reg8534.inc | 34 EEMWE avrbit EECR,2 ; EEPROM Master Write Enable
35 EERIE avrbit EECR,3 ; EEPROM Interrupt Enable
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| /dports/devel/avr-libc/avr-libc-2.0.0/libc/misc/ |
| H A D | eeupd_byte.S | 65 1: sbic _SFR_IO_ADDR (EECR), EEWE
78 sbi _SFR_IO_ADDR (EECR), EERE
92 out _SFR_IO_ADDR (EECR), __zero_reg__
100 sbi _SFR_IO_ADDR (EECR), EEMWE
101 sbi _SFR_IO_ADDR (EECR), EEWE
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| H A D | eedef.h | 52 # if !defined (EECR) && defined (DEECR) /* AT86RF401 */
53 # define EECR DEECR macro
76 # if !_SFR_IO_REG_P (EECR) \
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| H A D | eerd_block.S | 108 1: sbic _SFR_IO_ADDR (EECR), EEWE
116 sbi _SFR_IO_ADDR (EECR), EERE
133 1: sbic _SFR_IO_ADDR (EECR), EEWE
138 sbi _SFR_IO_ADDR (EECR), EERE
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| H A D | eewr_byte.S | 143 1: sbic _SFR_IO_ADDR (EECR), EEWE
148 out _SFR_IO_ADDR (EECR), __zero_reg__
165 sbi _SFR_IO_ADDR (EECR), EEMWE
166 sbi _SFR_IO_ADDR (EECR), EEWE
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| H A D | eerd_byte.S | 91 1: sbic _SFR_IO_ADDR (EECR), EEWE
102 sbi _SFR_IO_ADDR (EECR), EERE
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| /dports/devel/arduino-core/Arduino-b439a77/hardware/arduino/avr/bootloaders/atmega/ |
| H A D | ATmegaBOOT_168.c | 565 while(EECR & (1<<EEPE)); in main()
568 EECR |= (1<<EEMPE); in main()
569 EECR |= (1<<EEPE); in main()
587 while(bit_is_set(EECR,EEPE)); //Wait for previous EEPROM writes to complete in main()
589 while(bit_is_set(EECR,EEWE)); //Wait for previous EEPROM writes to complete in main()
719 while(EECR & (1<<EEPE)); in main()
721 EECR |= (1<<EERE); in main()
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| /dports/devel/arduino-core/Arduino-b439a77/hardware/arduino/avr/bootloaders/lilypad/src/ |
| H A D | ATmegaBOOT.c | 485 while(EECR & (1<<EEPE)); in main()
488 EECR |= (1<<EEMPE); in main()
489 EECR |= (1<<EEPE); in main()
507 while(bit_is_set(EECR,EEPE)); //Wait for previous EEPROM writes to complete in main()
638 while(EECR & (1<<EEPE)); in main()
640 EECR |= (1<<EERE); in main()
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| /dports/devel/arduino-core/Arduino-b439a77/hardware/arduino/avr/bootloaders/bt/ |
| H A D | ATmegaBOOT_168.c | 566 while(EECR & (1<<EEPE)); in main()
569 EECR |= (1<<EEMPE); in main()
570 EECR |= (1<<EEPE); in main()
588 while(bit_is_set(EECR,EEPE)); //Wait for previous EEPROM writes to complete in main()
716 while(EECR & (1<<EEPE)); in main()
718 EECR |= (1<<EERE); in main()
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| /dports/devel/avr-libc/avr-libc-2.0.0/include/avr/ |
| H A D | eeprom.h | 120 # define eeprom_is_ready() bit_is_clear (EECR, EEPE)
122 # define eeprom_is_ready() bit_is_clear (EECR, EEWE)
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| H A D | common.h | 156 # ifndef EECR
157 # define EECR _SFR_IO8(0x1C) macro
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| /dports/devel/avr-libc/avr-libc-2.0.0/ |
| H A D | ChangeLog-2005 | 1060 * include/avr/iom329.h: add bits for EECR.
1069 * include/avr/iomxx4.h: define the EECR bits.
1488 * include/avr/io1200.h (EECR, EEDR, EEAR, EEARL,
1490 * include/avr/io2313.h (EECR, EEDR, EEAR, EEARL,
1492 * include/avr/io2323.h (EECR, EEDR, EEAR, EEARL,
1494 * include/avr/io2333.h (EECR, EEDR, EEAR, EEARL,
1496 * include/avr/io2343.h (EECR, EEDR, EEAR, EEARL,
1498 * include/avr/io4414.h (EECR, EEDR, EEAR, EEARL,
1500 * include/avr/io4433.h (EECR, EEDR, EEAR, EEARL,
1502 * include/avr/io4434.h (EECR, EEDR, EEAR, EEARL,
[all …]
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