| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 262 FADDV_PRED, enumerator
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| H A D | AArch64SVEInstrInfo.td | 150 def AArch64faddv_p : SDNode<"AArch64ISD::FADDV_PRED", SDT_AArch64Reduce>;
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| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 262 FADDV_PRED, enumerator
|
| H A D | AArch64SVEInstrInfo.td | 150 def AArch64faddv_p : SDNode<"AArch64ISD::FADDV_PRED", SDT_AArch64Reduce>;
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 298 FADDV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 1737 MAKE_CASE(AArch64ISD::FADDV_PRED) in getTargetNodeName()
9971 return LowerReductionToSVE(AArch64ISD::FADDV_PRED, Op, DAG); in LowerVECREDUCE()
13122 return combineSVEReductionFP(N, AArch64ISD::FADDV_PRED, DAG); in performIntrinsicCombine()
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| H A D | AArch64SVEInstrInfo.td | 150 def AArch64faddv_p : SDNode<"AArch64ISD::FADDV_PRED", SDT_AArch64Reduce>;
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| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 300 FADDV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 1864 MAKE_CASE(AArch64ISD::FADDV_PRED) in getTargetNodeName()
10386 return LowerReductionToSVE(AArch64ISD::FADDV_PRED, Op, DAG); in LowerVECREDUCE()
13694 return combineSVEReductionFP(N, AArch64ISD::FADDV_PRED, DAG); in performIntrinsicCombine()
|
| H A D | AArch64SVEInstrInfo.td | 150 def AArch64faddv_p : SDNode<"AArch64ISD::FADDV_PRED", SDT_AArch64Reduce>;
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 300 FADDV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 1864 MAKE_CASE(AArch64ISD::FADDV_PRED) in getTargetNodeName()
10386 return LowerReductionToSVE(AArch64ISD::FADDV_PRED, Op, DAG); in LowerVECREDUCE()
13694 return combineSVEReductionFP(N, AArch64ISD::FADDV_PRED, DAG); in performIntrinsicCombine()
|
| H A D | AArch64SVEInstrInfo.td | 150 def AArch64faddv_p : SDNode<"AArch64ISD::FADDV_PRED", SDT_AArch64Reduce>;
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 313 FADDV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2037 MAKE_CASE(AArch64ISD::FADDV_PRED) in getTargetNodeName()
10981 return LowerReductionToSVE(AArch64ISD::FADDV_PRED, Op, DAG); in LowerVECREDUCE()
14519 return combineSVEReductionFP(N, AArch64ISD::FADDV_PRED, DAG); in performIntrinsicCombine()
16518 case AArch64ISD::FADDV_PRED: in isLanes1toNKnownZero()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 313 FADDV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2037 MAKE_CASE(AArch64ISD::FADDV_PRED) in getTargetNodeName()
10981 return LowerReductionToSVE(AArch64ISD::FADDV_PRED, Op, DAG); in LowerVECREDUCE()
14519 return combineSVEReductionFP(N, AArch64ISD::FADDV_PRED, DAG); in performIntrinsicCombine()
16518 case AArch64ISD::FADDV_PRED: in isLanes1toNKnownZero()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 313 FADDV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2037 MAKE_CASE(AArch64ISD::FADDV_PRED) in getTargetNodeName()
10981 return LowerReductionToSVE(AArch64ISD::FADDV_PRED, Op, DAG); in LowerVECREDUCE()
14519 return combineSVEReductionFP(N, AArch64ISD::FADDV_PRED, DAG); in performIntrinsicCombine()
16518 case AArch64ISD::FADDV_PRED: in isLanes1toNKnownZero()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 313 FADDV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2037 MAKE_CASE(AArch64ISD::FADDV_PRED) in getTargetNodeName()
10981 return LowerReductionToSVE(AArch64ISD::FADDV_PRED, Op, DAG); in LowerVECREDUCE()
14519 return combineSVEReductionFP(N, AArch64ISD::FADDV_PRED, DAG); in performIntrinsicCombine()
16518 case AArch64ISD::FADDV_PRED: in isLanes1toNKnownZero()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 313 FADDV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2037 MAKE_CASE(AArch64ISD::FADDV_PRED) in getTargetNodeName()
10981 return LowerReductionToSVE(AArch64ISD::FADDV_PRED, Op, DAG); in LowerVECREDUCE()
14519 return combineSVEReductionFP(N, AArch64ISD::FADDV_PRED, DAG); in performIntrinsicCombine()
16518 case AArch64ISD::FADDV_PRED: in isLanes1toNKnownZero()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 313 FADDV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2064 MAKE_CASE(AArch64ISD::FADDV_PRED) in getTargetNodeName()
11214 return LowerReductionToSVE(AArch64ISD::FADDV_PRED, Op, DAG); in LowerVECREDUCE()
14820 return combineSVEReductionFP(N, AArch64ISD::FADDV_PRED, DAG); in performIntrinsicCombine()
16818 case AArch64ISD::FADDV_PRED: in isLanes1toNKnownZero()
|