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Searched refs:FCR0_D (Results 1 – 22 of 22) sorted by relevance

/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-mips/
H A Dtranslate_init.c343 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
379 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
423 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
461 (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
582 (1 << FCR0_D) | (1 << FCR0_S) |
617 (1 << FCR0_D) | (1 << FCR0_S) |
651 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
693 (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) |
792 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
H A Dcpu.h110 #define FCR0_D 17 in run_dbwrap_watch1()
/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-mips/
H A Dtranslate_init.c343 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
379 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
423 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
461 (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
582 (1 << FCR0_D) | (1 << FCR0_S) |
617 (1 << FCR0_D) | (1 << FCR0_S) |
651 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
693 (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) |
792 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
H A Dcpu.h110 #define FCR0_D 17 macro
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/mips/
H A Dtranslate_init.inc.c244 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
443 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
483 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
642 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
686 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
718 (1 << FCR0_D) | (1 << FCR0_S) |
747 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
794 (1 << FCR0_D) | (1 << FCR0_S) |
831 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
871 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
[all …]
H A Dcpu.h63 #define FCR0_D 17 macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/mips/
H A Dtranslate_init.inc.c244 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
276 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
443 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
483 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
572 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
601 (1 << FCR0_D) | (1 << FCR0_S) |
630 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
677 (1 << FCR0_D) | (1 << FCR0_S) |
714 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
754 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
[all …]
H A Dcpu.h58 #define FCR0_D 17 macro
/dports/emulators/qemu42/qemu-4.2.1/target/mips/
H A Dtranslate_init.inc.c244 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
276 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
443 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
483 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
572 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
601 (1 << FCR0_D) | (1 << FCR0_S) |
630 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
677 (1 << FCR0_D) | (1 << FCR0_S) |
714 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
754 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
[all …]
H A Dcpu.h58 #define FCR0_D 17 macro
/dports/emulators/qemu-utils/qemu-4.2.1/target/mips/
H A Dtranslate_init.inc.c244 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
276 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
443 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
483 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
572 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
601 (1 << FCR0_D) | (1 << FCR0_S) |
630 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
677 (1 << FCR0_D) | (1 << FCR0_S) |
714 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
754 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
[all …]
H A Dcpu.h58 #define FCR0_D 17 macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/mips/
H A Dtranslate_init.inc.c244 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
276 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
318 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
443 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
483 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
571 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
600 (1 << FCR0_D) | (1 << FCR0_S) |
629 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
676 (1 << FCR0_D) | (1 << FCR0_S) |
713 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
[all …]
H A Dcpu.h62 #define FCR0_D 17 macro
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/mips/
H A Dcpu-defs.c.inc444 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
484 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
575 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
604 (1 << FCR0_D) | (1 << FCR0_S) |
633 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
680 (1 << FCR0_D) | (1 << FCR0_S) |
717 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
757 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
828 (0x1 << FCR0_D) | (0x1 << FCR0_S),
886 (0x1 << FCR0_D) | (0x1 << FCR0_S),
[all …]
H A Dcpu.h59 #define FCR0_D 17
/dports/emulators/qemu/qemu-6.2.0/target/mips/
H A Dcpu-defs.c.inc443 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
483 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
574 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
603 (1 << FCR0_D) | (1 << FCR0_S) |
632 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
679 (1 << FCR0_D) | (1 << FCR0_S) |
716 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
756 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
827 (0x1 << FCR0_D) | (0x1 << FCR0_S),
885 (0x1 << FCR0_D) | (0x1 << FCR0_S),
[all …]
H A Dcpu.h59 #define FCR0_D 17 macro
/dports/emulators/qemu60/qemu-6.0.0/target/mips/
H A Dcpu-defs.c.inc444 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
484 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
575 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
604 (1 << FCR0_D) | (1 << FCR0_S) |
633 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
680 (1 << FCR0_D) | (1 << FCR0_S) |
717 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
757 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
828 (0x1 << FCR0_D) | (0x1 << FCR0_S),
886 (0x1 << FCR0_D) | (0x1 << FCR0_S),
[all …]
H A Dcpu.h59 #define FCR0_D 17 macro
/dports/emulators/qemu5/qemu-5.2.0/target/mips/
H A Dtranslate_init.c.inc444 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
484 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
573 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
602 (1 << FCR0_D) | (1 << FCR0_S) |
631 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
678 (1 << FCR0_D) | (1 << FCR0_S) |
715 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
755 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
826 (0x1 << FCR0_D) | (0x1 << FCR0_S),
883 (0x1 << FCR0_D) | (0x1 << FCR0_S),
[all …]
H A Dcpu.h59 #define FCR0_D 17 macro