| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 266 FMINNMV_PRED, enumerator
|
| H A D | AArch64SVEInstrInfo.td | 154 def AArch64fminnmv_p : SDNode<"AArch64ISD::FMINNMV_PRED", SDT_AArch64Reduce>;
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 266 FMINNMV_PRED, enumerator
|
| H A D | AArch64SVEInstrInfo.td | 154 def AArch64fminnmv_p : SDNode<"AArch64ISD::FMINNMV_PRED", SDT_AArch64Reduce>;
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 302 FMINNMV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 1745 MAKE_CASE(AArch64ISD::FMINNMV_PRED) in getTargetNodeName()
9975 return LowerReductionToSVE(AArch64ISD::FMINNMV_PRED, Op, DAG); in LowerVECREDUCE()
13128 return combineSVEReductionFP(N, AArch64ISD::FMINNMV_PRED, DAG); in performIntrinsicCombine()
|
| H A D | AArch64SVEInstrInfo.td | 154 def AArch64fminnmv_p : SDNode<"AArch64ISD::FMINNMV_PRED", SDT_AArch64Reduce>;
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 304 FMINNMV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 1872 MAKE_CASE(AArch64ISD::FMINNMV_PRED) in getTargetNodeName()
10390 return LowerReductionToSVE(AArch64ISD::FMINNMV_PRED, Op, DAG); in LowerVECREDUCE()
13700 return combineSVEReductionFP(N, AArch64ISD::FMINNMV_PRED, DAG); in performIntrinsicCombine()
|
| H A D | AArch64SVEInstrInfo.td | 154 def AArch64fminnmv_p : SDNode<"AArch64ISD::FMINNMV_PRED", SDT_AArch64Reduce>;
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 304 FMINNMV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 1872 MAKE_CASE(AArch64ISD::FMINNMV_PRED) in getTargetNodeName()
10390 return LowerReductionToSVE(AArch64ISD::FMINNMV_PRED, Op, DAG); in LowerVECREDUCE()
13700 return combineSVEReductionFP(N, AArch64ISD::FMINNMV_PRED, DAG); in performIntrinsicCombine()
|
| H A D | AArch64SVEInstrInfo.td | 154 def AArch64fminnmv_p : SDNode<"AArch64ISD::FMINNMV_PRED", SDT_AArch64Reduce>;
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 317 FMINNMV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2047 MAKE_CASE(AArch64ISD::FMINNMV_PRED) in getTargetNodeName()
10985 return LowerReductionToSVE(AArch64ISD::FMINNMV_PRED, Op, DAG); in LowerVECREDUCE()
14525 return combineSVEReductionFP(N, AArch64ISD::FMINNMV_PRED, DAG); in performIntrinsicCombine()
16521 case AArch64ISD::FMINNMV_PRED: in isLanes1toNKnownZero()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 317 FMINNMV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2047 MAKE_CASE(AArch64ISD::FMINNMV_PRED) in getTargetNodeName()
10985 return LowerReductionToSVE(AArch64ISD::FMINNMV_PRED, Op, DAG); in LowerVECREDUCE()
14525 return combineSVEReductionFP(N, AArch64ISD::FMINNMV_PRED, DAG); in performIntrinsicCombine()
16521 case AArch64ISD::FMINNMV_PRED: in isLanes1toNKnownZero()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 317 FMINNMV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2047 MAKE_CASE(AArch64ISD::FMINNMV_PRED) in getTargetNodeName()
10985 return LowerReductionToSVE(AArch64ISD::FMINNMV_PRED, Op, DAG); in LowerVECREDUCE()
14525 return combineSVEReductionFP(N, AArch64ISD::FMINNMV_PRED, DAG); in performIntrinsicCombine()
16521 case AArch64ISD::FMINNMV_PRED: in isLanes1toNKnownZero()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 317 FMINNMV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2047 MAKE_CASE(AArch64ISD::FMINNMV_PRED) in getTargetNodeName()
10985 return LowerReductionToSVE(AArch64ISD::FMINNMV_PRED, Op, DAG); in LowerVECREDUCE()
14525 return combineSVEReductionFP(N, AArch64ISD::FMINNMV_PRED, DAG); in performIntrinsicCombine()
16521 case AArch64ISD::FMINNMV_PRED: in isLanes1toNKnownZero()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 317 FMINNMV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2047 MAKE_CASE(AArch64ISD::FMINNMV_PRED) in getTargetNodeName()
10985 return LowerReductionToSVE(AArch64ISD::FMINNMV_PRED, Op, DAG); in LowerVECREDUCE()
14525 return combineSVEReductionFP(N, AArch64ISD::FMINNMV_PRED, DAG); in performIntrinsicCombine()
16521 case AArch64ISD::FMINNMV_PRED: in isLanes1toNKnownZero()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 317 FMINNMV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2074 MAKE_CASE(AArch64ISD::FMINNMV_PRED) in getTargetNodeName()
11218 return LowerReductionToSVE(AArch64ISD::FMINNMV_PRED, Op, DAG); in LowerVECREDUCE()
14826 return combineSVEReductionFP(N, AArch64ISD::FMINNMV_PRED, DAG); in performIntrinsicCombine()
16821 case AArch64ISD::FMINNMV_PRED: in isLanes1toNKnownZero()
|