/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | legalize-fneg.mir | 14 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 15 ; SI: $vgpr0 = COPY [[FNEG]](s32) 18 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 19 ; VI: $vgpr0 = COPY [[FNEG]](s32) 23 ; GFX9: $vgpr0 = COPY [[FNEG]](s32) 37 ; SI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 41 ; VI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 45 ; GFX9: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 189 ; SI: $vgpr0 = COPY [[FNEG]](<2 x s16>) 193 ; VI: $vgpr0 = COPY [[FNEG]](<2 x s16>) [all …]
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H A D | legalize-fdiv.mir | 32 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 121 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 138 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 155 ; GFX9: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 214 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 233 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 362 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]] 386 ; VI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]] 466 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 502 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] [all …]
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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | legalize-fneg.mir | 14 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 15 ; SI: $vgpr0 = COPY [[FNEG]](s32) 18 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 19 ; VI: $vgpr0 = COPY [[FNEG]](s32) 23 ; GFX9: $vgpr0 = COPY [[FNEG]](s32) 37 ; SI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 41 ; VI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 45 ; GFX9: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 189 ; SI: $vgpr0 = COPY [[FNEG]](<2 x s16>) 193 ; VI: $vgpr0 = COPY [[FNEG]](<2 x s16>) [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | legalize-fneg.mir | 14 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 15 ; SI: $vgpr0 = COPY [[FNEG]](s32) 18 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 19 ; VI: $vgpr0 = COPY [[FNEG]](s32) 23 ; GFX9: $vgpr0 = COPY [[FNEG]](s32) 37 ; SI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 41 ; VI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 45 ; GFX9: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 189 ; SI: $vgpr0 = COPY [[FNEG]](<2 x s16>) 193 ; VI: $vgpr0 = COPY [[FNEG]](<2 x s16>) [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | legalize-fneg.mir | 15 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 16 ; SI: $vgpr0 = COPY [[FNEG]](s32) 19 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 20 ; VI: $vgpr0 = COPY [[FNEG]](s32) 24 ; GFX9: $vgpr0 = COPY [[FNEG]](s32) 38 ; SI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 42 ; VI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 46 ; GFX9: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 190 ; SI: $vgpr0 = COPY [[FNEG]](<2 x s16>) 194 ; VI: $vgpr0 = COPY [[FNEG]](<2 x s16>) [all …]
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H A D | legalize-fdiv.mir | 32 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 121 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 138 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 155 ; GFX9: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 214 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 233 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 252 ; GFX9: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 414 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]] 438 ; VI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]] 526 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] [all …]
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | legalize-fneg.mir | 14 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 15 ; SI: $vgpr0 = COPY [[FNEG]](s32) 18 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 19 ; VI: $vgpr0 = COPY [[FNEG]](s32) 23 ; GFX9: $vgpr0 = COPY [[FNEG]](s32) 37 ; SI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 41 ; VI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 45 ; GFX9: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 189 ; SI: $vgpr0 = COPY [[FNEG]](<2 x s16>) 193 ; VI: $vgpr0 = COPY [[FNEG]](<2 x s16>) [all …]
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/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | legalize-fneg.mir | 14 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 15 ; SI: $vgpr0 = COPY [[FNEG]](s32) 18 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 19 ; VI: $vgpr0 = COPY [[FNEG]](s32) 23 ; GFX9: $vgpr0 = COPY [[FNEG]](s32) 36 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY]] 37 ; SI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 40 ; VI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY]] 41 ; VI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 45 ; GFX9: $vgpr0_vgpr1 = COPY [[FNEG]](s64) [all …]
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H A D | legalize-fsub.mir | 41 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]] 47 ; VI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]] 53 ; GFX9: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]] 71 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]] 77 ; VI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]] 104 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FPEXT]] 117 ; VI: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[TRUNC1]] 271 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[UV2]] 282 ; VI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[UV2]] 336 ; VI: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[UV]] [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | legalize-fneg.mir | 14 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 15 ; SI: $vgpr0 = COPY [[FNEG]](s32) 18 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 19 ; VI: $vgpr0 = COPY [[FNEG]](s32) 23 ; GFX9: $vgpr0 = COPY [[FNEG]](s32) 37 ; SI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 41 ; VI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 45 ; GFX9: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 189 ; SI: $vgpr0 = COPY [[FNEG]](<2 x s16>) 193 ; VI: $vgpr0 = COPY [[FNEG]](<2 x s16>) [all …]
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H A D | legalize-fdiv.mir | 32 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 121 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 138 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 155 ; GFX9: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 214 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 233 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 362 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]] 386 ; VI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]] 466 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 502 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | legalize-fneg.mir | 15 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 16 ; SI: $vgpr0 = COPY [[FNEG]](s32) 19 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 20 ; VI: $vgpr0 = COPY [[FNEG]](s32) 24 ; GFX9: $vgpr0 = COPY [[FNEG]](s32) 38 ; SI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 42 ; VI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 46 ; GFX9: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 190 ; SI: $vgpr0 = COPY [[FNEG]](<2 x s16>) 194 ; VI: $vgpr0 = COPY [[FNEG]](<2 x s16>) [all …]
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H A D | legalize-fdiv.mir | 32 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 121 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 138 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 155 ; GFX9: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 214 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 233 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 252 ; GFX9: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 414 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]] 438 ; VI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]] 526 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | legalize-fneg.mir | 15 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 16 ; SI: $vgpr0 = COPY [[FNEG]](s32) 19 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 20 ; VI: $vgpr0 = COPY [[FNEG]](s32) 24 ; GFX9: $vgpr0 = COPY [[FNEG]](s32) 38 ; SI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 42 ; VI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 46 ; GFX9: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 190 ; SI: $vgpr0 = COPY [[FNEG]](<2 x s16>) 194 ; VI: $vgpr0 = COPY [[FNEG]](<2 x s16>) [all …]
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H A D | legalize-fdiv.mir | 32 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 121 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 138 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 155 ; GFX9: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 214 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 233 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 252 ; GFX9: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 414 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]] 438 ; VI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]] 526 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | legalize-fneg.mir | 14 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 15 ; SI: $vgpr0 = COPY [[FNEG]](s32) 18 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 19 ; VI: $vgpr0 = COPY [[FNEG]](s32) 23 ; GFX9: $vgpr0 = COPY [[FNEG]](s32) 37 ; SI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 41 ; VI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 45 ; GFX9: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 189 ; SI: $vgpr0 = COPY [[FNEG]](<2 x s16>) 193 ; VI: $vgpr0 = COPY [[FNEG]](<2 x s16>) [all …]
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H A D | legalize-fdiv.mir | 32 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 121 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 138 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 155 ; GFX9: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 214 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 233 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 252 ; GFX9: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 414 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]] 438 ; VI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]] 526 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] [all …]
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | legalize-fneg.mir | 15 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 16 ; SI: $vgpr0 = COPY [[FNEG]](s32) 19 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 20 ; VI: $vgpr0 = COPY [[FNEG]](s32) 24 ; GFX9: $vgpr0 = COPY [[FNEG]](s32) 38 ; SI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 42 ; VI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 46 ; GFX9: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 190 ; SI: $vgpr0 = COPY [[FNEG]](<2 x s16>) 194 ; VI: $vgpr0 = COPY [[FNEG]](<2 x s16>) [all …]
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H A D | legalize-fdiv.mir | 32 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 121 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 138 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 155 ; GFX9: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 214 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 233 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 252 ; GFX9: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 414 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]] 438 ; VI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]] 526 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | legalize-fneg.mir | 15 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 16 ; SI: $vgpr0 = COPY [[FNEG]](s32) 19 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 20 ; VI: $vgpr0 = COPY [[FNEG]](s32) 24 ; GFX9: $vgpr0 = COPY [[FNEG]](s32) 38 ; SI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 42 ; VI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 46 ; GFX9: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 190 ; SI: $vgpr0 = COPY [[FNEG]](<2 x s16>) 194 ; VI: $vgpr0 = COPY [[FNEG]](<2 x s16>) [all …]
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H A D | legalize-fdiv.mir | 32 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 121 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 138 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 155 ; GFX9: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 214 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 233 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 252 ; GFX9: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 414 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]] 438 ; VI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]] 526 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | legalize-fneg.mir | 14 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 15 ; SI: $vgpr0 = COPY [[FNEG]](s32) 18 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 19 ; VI: $vgpr0 = COPY [[FNEG]](s32) 23 ; GFX9: $vgpr0 = COPY [[FNEG]](s32) 37 ; SI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 41 ; VI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 45 ; GFX9: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 189 ; SI: $vgpr0 = COPY [[FNEG]](<2 x s16>) 193 ; VI: $vgpr0 = COPY [[FNEG]](<2 x s16>) [all …]
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H A D | legalize-fdiv.mir | 32 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 121 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 138 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 155 ; GFX9: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 214 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 233 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 252 ; GFX9: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 414 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]] 438 ; VI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]] 526 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | legalize-fneg.mir | 15 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 16 ; SI: $vgpr0 = COPY [[FNEG]](s32) 19 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] 20 ; VI: $vgpr0 = COPY [[FNEG]](s32) 24 ; GFX9: $vgpr0 = COPY [[FNEG]](s32) 38 ; SI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 42 ; VI: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 46 ; GFX9: $vgpr0_vgpr1 = COPY [[FNEG]](s64) 190 ; SI: $vgpr0 = COPY [[FNEG]](<2 x s16>) 194 ; VI: $vgpr0 = COPY [[FNEG]](<2 x s16>) [all …]
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H A D | legalize-fdiv.mir | 32 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 121 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 138 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 155 ; GFX9: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 214 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 233 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 252 ; GFX9: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] 414 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]] 438 ; VI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]] 526 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] [all …]
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