| /dports/audio/lsp-plugins-lv2/lsp-plugins-1.1.31/include/dsp/arch/aarch64/ |
| H A D | fpcr.h | 40 #define FPCR_DN (1 << 25) /* Default NaN mode control */ macro
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| /dports/audio/tamgamp-lv2/tamgamp.lv2-590ced0a1da96ca481a1a719eebdb17f3af472e4/include/dsp/arch/aarch64/ |
| H A D | fpcr.h | 40 #define FPCR_DN (1 << 25) /* Default NaN mode control */
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| /dports/audio/lsp-plugins-lv2/lsp-plugins-1.1.31/src/dsp/ |
| H A D | aarch64.cpp | 310 write_fpcr(fpcr | FPCR_FZ | FPCR_DN | FPCR_FZ16); in start()
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| /dports/audio/tamgamp-lv2/tamgamp.lv2-590ced0a1da96ca481a1a719eebdb17f3af472e4/src/dsp/ |
| H A D | aarch64.cpp | 305 write_fpcr(fpcr | FPCR_FZ | FPCR_DN | FPCR_FZ16); in start()
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| /dports/misc/rump/buildrump.sh-b914579/src/sys/arch/aarch64/include/ |
| H A D | armreg.h | 98 FPCR_DN = __BIT(25), // Default Nan Control variable
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| /dports/emulators/qemu-utils/qemu-4.2.1/target/arm/ |
| H A D | vfp_helper.c | 134 if (changed & FPCR_DN) { in vfp_set_fpscr_to_host()
135 bool dnan_enabled = val & FPCR_DN; in vfp_set_fpscr_to_host()
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| H A D | cpu.h | 1444 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ macro
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| /dports/emulators/qemu5/qemu-5.2.0/target/arm/ |
| H A D | vfp_helper.c | 138 if (changed & FPCR_DN) { in vfp_set_fpscr_to_host()
139 bool dnan_enabled = val & FPCR_DN; in vfp_set_fpscr_to_host()
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| H A D | cpu.h | 1525 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ macro
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| /dports/emulators/qemu42/qemu-4.2.1/target/arm/ |
| H A D | vfp_helper.c | 134 if (changed & FPCR_DN) { in vfp_set_fpscr_to_host()
135 bool dnan_enabled = val & FPCR_DN; in vfp_set_fpscr_to_host()
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| H A D | cpu.h | 1444 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ macro
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| /dports/emulators/qemu60/qemu-6.0.0/target/arm/ |
| H A D | vfp_helper.c | 138 if (changed & FPCR_DN) { in vfp_set_fpscr_to_host()
139 bool dnan_enabled = val & FPCR_DN; in vfp_set_fpscr_to_host()
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| H A D | cpu.h | 1548 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ macro
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/ |
| H A D | vfp_helper.c | 134 if (changed & FPCR_DN) { in vfp_set_fpscr_to_host()
135 bool dnan_enabled = val & FPCR_DN; in vfp_set_fpscr_to_host()
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| H A D | cpu.h | 1492 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ macro
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| /dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/ |
| H A D | vfp_helper.c | 138 if (changed & FPCR_DN) { in vfp_set_fpscr_to_host()
139 bool dnan_enabled = val & FPCR_DN; in vfp_set_fpscr_to_host()
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| H A D | cpu.h | 1569 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ macro
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| /dports/emulators/qemu/qemu-6.2.0/target/arm/ |
| H A D | vfp_helper.c | 138 if (changed & FPCR_DN) { in vfp_set_fpscr_to_host()
139 bool dnan_enabled = val & FPCR_DN; in vfp_set_fpscr_to_host()
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| H A D | cpu.h | 1569 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ macro
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| /dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/ |
| H A D | vfp_helper.c | 134 if (changed & FPCR_DN) { in vfp_set_fpscr_to_host()
135 bool dnan_enabled = val & FPCR_DN; in vfp_set_fpscr_to_host()
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| H A D | cpu.h | 1492 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ macro
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| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/ |
| H A D | cpu.h | 1288 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ macro
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| /dports/emulators/qemu/qemu-6.2.0/hw/intc/ |
| H A D | armv7m_nvic.c | 2134 uint32_t mask = FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK; in nvic_writel()
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| /dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/intc/ |
| H A D | armv7m_nvic.c | 2134 uint32_t mask = FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK; in nvic_writel()
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| /dports/emulators/qemu60/qemu-6.0.0/hw/intc/ |
| H A D | armv7m_nvic.c | 2119 uint32_t mask = FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK; in nvic_writel()
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