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Searched refs:FPGA_MAIN_CFG_BASE (Results 1 – 7 of 7) sorted by relevance

/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/include/configs/
H A Dhymod.h664 #define FPGA_MAIN_CFG_BASE (CONFIG_SYS_FPGA_BASE) macro
666 #define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
674 #define CONFIG_SYS_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/include/configs/
H A Dhymod.h664 #define FPGA_MAIN_CFG_BASE (CONFIG_SYS_FPGA_BASE) macro
666 #define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
674 #define CONFIG_SYS_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/include/configs/
H A Dhymod.h664 #define FPGA_MAIN_CFG_BASE (CONFIG_SYS_FPGA_BASE) macro
666 #define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
674 #define CONFIG_SYS_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/include/configs/
H A Dhymod.h664 #define FPGA_MAIN_CFG_BASE (CONFIG_SYS_FPGA_BASE) macro
666 #define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
674 #define CONFIG_SYS_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/include/configs/
H A Dhymod.h664 #define FPGA_MAIN_CFG_BASE (CONFIG_SYS_FPGA_BASE) macro
666 #define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
674 #define CONFIG_SYS_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/include/configs/
H A Dhymod.h664 #define FPGA_MAIN_CFG_BASE (CONFIG_SYS_FPGA_BASE) macro
666 #define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
674 #define CONFIG_SYS_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/include/configs/
H A Dhymod.h664 #define FPGA_MAIN_CFG_BASE (CONFIG_SYS_FPGA_BASE) macro
666 #define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
674 #define CONFIG_SYS_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)