/dports/emulators/qemu42/qemu-4.2.1/include/hw/arm/ |
H A D | fsl-imx6ul.h | 55 FSL_IMX6UL_NUM_ECSPIS = 4, enumerator 74 IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
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/dports/emulators/qemu/qemu-6.2.0/include/hw/arm/ |
H A D | fsl-imx6ul.h | 58 FSL_IMX6UL_NUM_ECSPIS = 4, enumerator 79 IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
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/dports/emulators/qemu60/qemu-6.0.0/include/hw/arm/ |
H A D | fsl-imx6ul.h | 58 FSL_IMX6UL_NUM_ECSPIS = 4, enumerator 79 IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/include/hw/arm/ |
H A D | fsl-imx6ul.h | 55 FSL_IMX6UL_NUM_ECSPIS = 4, enumerator 74 IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
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/dports/emulators/qemu5/qemu-5.2.0/include/hw/arm/ |
H A D | fsl-imx6ul.h | 58 FSL_IMX6UL_NUM_ECSPIS = 4, enumerator 79 IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
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/dports/emulators/qemu-utils/qemu-4.2.1/include/hw/arm/ |
H A D | fsl-imx6ul.h | 55 FSL_IMX6UL_NUM_ECSPIS = 4, enumerator 74 IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/include/hw/arm/ |
H A D | fsl-imx6ul.h | 57 FSL_IMX6UL_NUM_ECSPIS = 4, 78 IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/include/hw/arm/ |
H A D | fsl-imx6ul.h | 58 FSL_IMX6UL_NUM_ECSPIS = 4, enumerator 79 IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/include/hw/arm/ |
H A D | fsl-imx6ul.h | 57 FSL_IMX6UL_NUM_ECSPIS = 4, enumerator 78 IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
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/dports/emulators/qemu42/qemu-4.2.1/hw/arm/ |
H A D | fsl-imx6ul.c | 103 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_init() 328 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_realize() 329 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize() 336 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
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/dports/emulators/qemu-utils/qemu-4.2.1/hw/arm/ |
H A D | fsl-imx6ul.c | 103 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_init() 328 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_realize() 329 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize() 336 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/arm/ |
H A D | fsl-imx6ul.c | 105 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_init() 350 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_realize() 351 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize() 358 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
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/dports/emulators/qemu/qemu-6.2.0/hw/arm/ |
H A D | fsl-imx6ul.c | 98 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_init() 320 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_realize() 321 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize() 328 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
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/dports/emulators/qemu60/qemu-6.0.0/hw/arm/ |
H A D | fsl-imx6ul.c | 98 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_init() 320 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_realize() 321 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize() 328 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
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/dports/emulators/qemu5/qemu-5.2.0/hw/arm/ |
H A D | fsl-imx6ul.c | 98 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_init() 320 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_realize() 321 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize() 328 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/arm/ |
H A D | fsl-imx6ul.c | 104 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_init() 341 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_realize() 342 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize() 349 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/arm/ |
H A D | fsl-imx6ul.c | 104 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_init() 341 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_realize() 342 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize() 349 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/arm/ |
H A D | fsl-imx6ul.c | 98 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_init() 320 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_realize() 321 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize() 328 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
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