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Searched refs:FSL_IMX6UL_NUM_ECSPIS (Results 1 – 18 of 18) sorted by relevance

/dports/emulators/qemu42/qemu-4.2.1/include/hw/arm/
H A Dfsl-imx6ul.h55 FSL_IMX6UL_NUM_ECSPIS = 4, enumerator
74 IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
/dports/emulators/qemu/qemu-6.2.0/include/hw/arm/
H A Dfsl-imx6ul.h58 FSL_IMX6UL_NUM_ECSPIS = 4, enumerator
79 IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
/dports/emulators/qemu60/qemu-6.0.0/include/hw/arm/
H A Dfsl-imx6ul.h58 FSL_IMX6UL_NUM_ECSPIS = 4, enumerator
79 IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/include/hw/arm/
H A Dfsl-imx6ul.h55 FSL_IMX6UL_NUM_ECSPIS = 4, enumerator
74 IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
/dports/emulators/qemu5/qemu-5.2.0/include/hw/arm/
H A Dfsl-imx6ul.h58 FSL_IMX6UL_NUM_ECSPIS = 4, enumerator
79 IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
/dports/emulators/qemu-utils/qemu-4.2.1/include/hw/arm/
H A Dfsl-imx6ul.h55 FSL_IMX6UL_NUM_ECSPIS = 4, enumerator
74 IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
/dports/emulators/qemu-guest-agent/qemu-5.0.1/include/hw/arm/
H A Dfsl-imx6ul.h57 FSL_IMX6UL_NUM_ECSPIS = 4,
78 IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/include/hw/arm/
H A Dfsl-imx6ul.h58 FSL_IMX6UL_NUM_ECSPIS = 4, enumerator
79 IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/include/hw/arm/
H A Dfsl-imx6ul.h57 FSL_IMX6UL_NUM_ECSPIS = 4, enumerator
78 IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
/dports/emulators/qemu42/qemu-4.2.1/hw/arm/
H A Dfsl-imx6ul.c103 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_init()
328 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_realize()
329 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
336 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
/dports/emulators/qemu-utils/qemu-4.2.1/hw/arm/
H A Dfsl-imx6ul.c103 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_init()
328 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_realize()
329 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
336 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/arm/
H A Dfsl-imx6ul.c105 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_init()
350 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_realize()
351 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
358 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
/dports/emulators/qemu/qemu-6.2.0/hw/arm/
H A Dfsl-imx6ul.c98 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_init()
320 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_realize()
321 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
328 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
/dports/emulators/qemu60/qemu-6.0.0/hw/arm/
H A Dfsl-imx6ul.c98 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_init()
320 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_realize()
321 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
328 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
/dports/emulators/qemu5/qemu-5.2.0/hw/arm/
H A Dfsl-imx6ul.c98 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_init()
320 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_realize()
321 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
328 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/arm/
H A Dfsl-imx6ul.c104 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_init()
341 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_realize()
342 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
349 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/arm/
H A Dfsl-imx6ul.c104 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_init()
341 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_realize()
342 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
349 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/arm/
H A Dfsl-imx6ul.c98 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_init()
320 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { in fsl_imx6ul_realize()
321 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()
328 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { in fsl_imx6ul_realize()