Home
last modified time | relevance | path

Searched refs:FSL_IMX6UL_NUM_I2CS (Results 1 – 18 of 18) sorted by relevance

/dports/emulators/qemu42/qemu-4.2.1/include/hw/arm/
H A Dfsl-imx6ul.h54 FSL_IMX6UL_NUM_I2CS = 4, enumerator
75 IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
/dports/emulators/qemu/qemu-6.2.0/include/hw/arm/
H A Dfsl-imx6ul.h57 FSL_IMX6UL_NUM_I2CS = 4, enumerator
80 IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
/dports/emulators/qemu60/qemu-6.0.0/include/hw/arm/
H A Dfsl-imx6ul.h57 FSL_IMX6UL_NUM_I2CS = 4, enumerator
80 IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/include/hw/arm/
H A Dfsl-imx6ul.h54 FSL_IMX6UL_NUM_I2CS = 4, enumerator
75 IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
/dports/emulators/qemu5/qemu-5.2.0/include/hw/arm/
H A Dfsl-imx6ul.h57 FSL_IMX6UL_NUM_I2CS = 4, enumerator
80 IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
/dports/emulators/qemu-utils/qemu-4.2.1/include/hw/arm/
H A Dfsl-imx6ul.h54 FSL_IMX6UL_NUM_I2CS = 4, enumerator
75 IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
/dports/emulators/qemu-guest-agent/qemu-5.0.1/include/hw/arm/
H A Dfsl-imx6ul.h56 FSL_IMX6UL_NUM_I2CS = 4,
79 IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/include/hw/arm/
H A Dfsl-imx6ul.h57 FSL_IMX6UL_NUM_I2CS = 4, enumerator
80 IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/include/hw/arm/
H A Dfsl-imx6ul.h56 FSL_IMX6UL_NUM_I2CS = 4, enumerator
79 IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
/dports/emulators/qemu42/qemu-4.2.1/hw/arm/
H A Dfsl-imx6ul.c112 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_init()
358 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_realize()
359 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
366 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
/dports/emulators/qemu-utils/qemu-4.2.1/hw/arm/
H A Dfsl-imx6ul.c112 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_init()
358 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_realize()
359 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
366 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/arm/
H A Dfsl-imx6ul.c114 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_init()
380 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_realize()
381 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
388 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
/dports/emulators/qemu/qemu-6.2.0/hw/arm/
H A Dfsl-imx6ul.c106 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_init()
349 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_realize()
350 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
357 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
/dports/emulators/qemu60/qemu-6.0.0/hw/arm/
H A Dfsl-imx6ul.c106 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_init()
349 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_realize()
350 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
357 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
/dports/emulators/qemu5/qemu-5.2.0/hw/arm/
H A Dfsl-imx6ul.c106 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_init()
349 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_realize()
350 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
357 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/arm/
H A Dfsl-imx6ul.c113 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_init()
371 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_realize()
372 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
379 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/arm/
H A Dfsl-imx6ul.c113 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_init()
371 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_realize()
372 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
379 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/arm/
H A Dfsl-imx6ul.c106 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_init()
349 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_realize()
350 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
357 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()