/dports/emulators/qemu42/qemu-4.2.1/include/hw/arm/ |
H A D | fsl-imx6ul.h | 54 FSL_IMX6UL_NUM_I2CS = 4, enumerator 75 IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
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/dports/emulators/qemu/qemu-6.2.0/include/hw/arm/ |
H A D | fsl-imx6ul.h | 57 FSL_IMX6UL_NUM_I2CS = 4, enumerator 80 IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
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/dports/emulators/qemu60/qemu-6.0.0/include/hw/arm/ |
H A D | fsl-imx6ul.h | 57 FSL_IMX6UL_NUM_I2CS = 4, enumerator 80 IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/include/hw/arm/ |
H A D | fsl-imx6ul.h | 54 FSL_IMX6UL_NUM_I2CS = 4, enumerator 75 IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
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/dports/emulators/qemu5/qemu-5.2.0/include/hw/arm/ |
H A D | fsl-imx6ul.h | 57 FSL_IMX6UL_NUM_I2CS = 4, enumerator 80 IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
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/dports/emulators/qemu-utils/qemu-4.2.1/include/hw/arm/ |
H A D | fsl-imx6ul.h | 54 FSL_IMX6UL_NUM_I2CS = 4, enumerator 75 IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/include/hw/arm/ |
H A D | fsl-imx6ul.h | 56 FSL_IMX6UL_NUM_I2CS = 4, 79 IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/include/hw/arm/ |
H A D | fsl-imx6ul.h | 57 FSL_IMX6UL_NUM_I2CS = 4, enumerator 80 IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/include/hw/arm/ |
H A D | fsl-imx6ul.h | 56 FSL_IMX6UL_NUM_I2CS = 4, enumerator 79 IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
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/dports/emulators/qemu42/qemu-4.2.1/hw/arm/ |
H A D | fsl-imx6ul.c | 112 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_init() 358 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_realize() 359 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize() 366 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
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/dports/emulators/qemu-utils/qemu-4.2.1/hw/arm/ |
H A D | fsl-imx6ul.c | 112 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_init() 358 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_realize() 359 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize() 366 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/arm/ |
H A D | fsl-imx6ul.c | 114 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_init() 380 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_realize() 381 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize() 388 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
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/dports/emulators/qemu/qemu-6.2.0/hw/arm/ |
H A D | fsl-imx6ul.c | 106 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_init() 349 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_realize() 350 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize() 357 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
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/dports/emulators/qemu60/qemu-6.0.0/hw/arm/ |
H A D | fsl-imx6ul.c | 106 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_init() 349 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_realize() 350 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize() 357 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
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/dports/emulators/qemu5/qemu-5.2.0/hw/arm/ |
H A D | fsl-imx6ul.c | 106 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_init() 349 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_realize() 350 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize() 357 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/arm/ |
H A D | fsl-imx6ul.c | 113 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_init() 371 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_realize() 372 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize() 379 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/arm/ |
H A D | fsl-imx6ul.c | 113 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_init() 371 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_realize() 372 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize() 379 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/arm/ |
H A D | fsl-imx6ul.c | 106 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_init() 349 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { in fsl_imx6ul_realize() 350 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize() 357 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { in fsl_imx6ul_realize()
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