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Searched refs:GLD1_UXTW_MERGE_ZERO (Results 1 – 25 of 33) sorted by relevance

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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h294 GLD1_UXTW_MERGE_ZERO, enumerator
H A DAArch64ISelLowering.cpp1562 MAKE_CASE(AArch64ISD::GLD1_UXTW_MERGE_ZERO) in getTargetNodeName()
11032 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSVEAndCombine()
13617 ? AArch64ISD::GLD1_UXTW_MERGE_ZERO in performGatherLoadCombine()
13739 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSignExtendInRegCombine()
13987 return performGatherLoadCombine(N, DAG, AArch64ISD::GLD1_UXTW_MERGE_ZERO, in PerformDAGCombine()
H A DAArch64SVEInstrInfo.td71 def AArch64ld1_gather_uxtw_z : SDNode<"AArch64ISD::GLD1_UXTW_MERGE_ZERO", SDT_AArch64…
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/
H A DAArch64ISelLowering.h294 GLD1_UXTW_MERGE_ZERO, enumerator
H A DAArch64ISelLowering.cpp1565 MAKE_CASE(AArch64ISD::GLD1_UXTW_MERGE_ZERO) in getTargetNodeName()
11064 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSVEAndCombine()
13652 ? AArch64ISD::GLD1_UXTW_MERGE_ZERO in performGatherLoadCombine()
13774 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSignExtendInRegCombine()
14022 return performGatherLoadCombine(N, DAG, AArch64ISD::GLD1_UXTW_MERGE_ZERO, in PerformDAGCombine()
H A DAArch64SVEInstrInfo.td71 def AArch64ld1_gather_uxtw_z : SDNode<"AArch64ISD::GLD1_UXTW_MERGE_ZERO", SDT_AArch64…
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h330 GLD1_UXTW_MERGE_ZERO, enumerator
H A DAArch64ISelLowering.cpp1818 MAKE_CASE(AArch64ISD::GLD1_UXTW_MERGE_ZERO) in getTargetNodeName()
11931 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSVEAndCombine()
14746 ? AArch64ISD::GLD1_UXTW_MERGE_ZERO in performGatherLoadCombine()
14866 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSignExtendInRegCombine()
15124 return performGatherLoadCombine(N, DAG, AArch64ISD::GLD1_UXTW_MERGE_ZERO, in PerformDAGCombine()
H A DAArch64SVEInstrInfo.td71 def AArch64ld1_gather_uxtw_z : SDNode<"AArch64ISD::GLD1_UXTW_MERGE_ZERO", SDT_AArch64…
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h337 GLD1_UXTW_MERGE_ZERO, enumerator
H A DAArch64ISelLowering.cpp1945 MAKE_CASE(AArch64ISD::GLD1_UXTW_MERGE_ZERO) in getTargetNodeName()
3846 AArch64ISD::GLD1_UXTW_MERGE_ZERO}, in getGatherVecOpcode()
3896 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in getSignExtendedGatherOpcode()
12503 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSVEAndCombine()
15366 ? AArch64ISD::GLD1_UXTW_MERGE_ZERO in performGatherLoadCombine()
15489 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSignExtendInRegCombine()
15750 return performGatherLoadCombine(N, DAG, AArch64ISD::GLD1_UXTW_MERGE_ZERO, in PerformDAGCombine()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h337 GLD1_UXTW_MERGE_ZERO, enumerator
H A DAArch64ISelLowering.cpp1945 MAKE_CASE(AArch64ISD::GLD1_UXTW_MERGE_ZERO) in getTargetNodeName()
3846 AArch64ISD::GLD1_UXTW_MERGE_ZERO}, in getGatherVecOpcode()
3896 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in getSignExtendedGatherOpcode()
12503 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSVEAndCombine()
15366 ? AArch64ISD::GLD1_UXTW_MERGE_ZERO in performGatherLoadCombine()
15489 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSignExtendInRegCombine()
15750 return performGatherLoadCombine(N, DAG, AArch64ISD::GLD1_UXTW_MERGE_ZERO, in PerformDAGCombine()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h354 GLD1_UXTW_MERGE_ZERO, enumerator
H A DAArch64ISelLowering.cpp2122 MAKE_CASE(AArch64ISD::GLD1_UXTW_MERGE_ZERO) in getTargetNodeName()
4180 AArch64ISD::GLD1_UXTW_MERGE_ZERO}, in getGatherVecOpcode()
4230 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in getSignExtendedGatherOpcode()
13217 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSVEAndCombine()
15042 Opc == AArch64ISD::GLD1_UXTW_MERGE_ZERO || in performGLD1Combine()
16283 ? AArch64ISD::GLD1_UXTW_MERGE_ZERO in performGatherLoadCombine()
16406 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSignExtendInRegCombine()
16673 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in PerformDAGCombine()
16779 return performGatherLoadCombine(N, DAG, AArch64ISD::GLD1_UXTW_MERGE_ZERO, in PerformDAGCombine()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/
H A DAArch64ISelLowering.h354 GLD1_UXTW_MERGE_ZERO, enumerator
H A DAArch64ISelLowering.cpp2122 MAKE_CASE(AArch64ISD::GLD1_UXTW_MERGE_ZERO) in getTargetNodeName()
4180 AArch64ISD::GLD1_UXTW_MERGE_ZERO}, in getGatherVecOpcode()
4230 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in getSignExtendedGatherOpcode()
13217 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSVEAndCombine()
15042 Opc == AArch64ISD::GLD1_UXTW_MERGE_ZERO || in performGLD1Combine()
16283 ? AArch64ISD::GLD1_UXTW_MERGE_ZERO in performGatherLoadCombine()
16406 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSignExtendInRegCombine()
16673 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in PerformDAGCombine()
16779 return performGatherLoadCombine(N, DAG, AArch64ISD::GLD1_UXTW_MERGE_ZERO, in PerformDAGCombine()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h354 GLD1_UXTW_MERGE_ZERO, enumerator
H A DAArch64ISelLowering.cpp2122 MAKE_CASE(AArch64ISD::GLD1_UXTW_MERGE_ZERO) in getTargetNodeName()
4180 AArch64ISD::GLD1_UXTW_MERGE_ZERO}, in getGatherVecOpcode()
4230 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in getSignExtendedGatherOpcode()
13217 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSVEAndCombine()
15042 Opc == AArch64ISD::GLD1_UXTW_MERGE_ZERO || in performGLD1Combine()
16283 ? AArch64ISD::GLD1_UXTW_MERGE_ZERO in performGatherLoadCombine()
16406 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSignExtendInRegCombine()
16673 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in PerformDAGCombine()
16779 return performGatherLoadCombine(N, DAG, AArch64ISD::GLD1_UXTW_MERGE_ZERO, in PerformDAGCombine()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h354 GLD1_UXTW_MERGE_ZERO, enumerator
H A DAArch64ISelLowering.cpp2122 MAKE_CASE(AArch64ISD::GLD1_UXTW_MERGE_ZERO) in getTargetNodeName()
4180 AArch64ISD::GLD1_UXTW_MERGE_ZERO}, in getGatherVecOpcode()
4230 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in getSignExtendedGatherOpcode()
13217 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSVEAndCombine()
15042 Opc == AArch64ISD::GLD1_UXTW_MERGE_ZERO || in performGLD1Combine()
16283 ? AArch64ISD::GLD1_UXTW_MERGE_ZERO in performGatherLoadCombine()
16406 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSignExtendInRegCombine()
16673 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in PerformDAGCombine()
16779 return performGatherLoadCombine(N, DAG, AArch64ISD::GLD1_UXTW_MERGE_ZERO, in PerformDAGCombine()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h354 GLD1_UXTW_MERGE_ZERO, enumerator
H A DAArch64ISelLowering.cpp2122 MAKE_CASE(AArch64ISD::GLD1_UXTW_MERGE_ZERO) in getTargetNodeName()
4180 AArch64ISD::GLD1_UXTW_MERGE_ZERO}, in getGatherVecOpcode()
4230 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in getSignExtendedGatherOpcode()
13217 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSVEAndCombine()
15042 Opc == AArch64ISD::GLD1_UXTW_MERGE_ZERO || in performGLD1Combine()
16283 ? AArch64ISD::GLD1_UXTW_MERGE_ZERO in performGatherLoadCombine()
16406 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSignExtendInRegCombine()
16673 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in PerformDAGCombine()
16779 return performGatherLoadCombine(N, DAG, AArch64ISD::GLD1_UXTW_MERGE_ZERO, in PerformDAGCombine()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h354 GLD1_UXTW_MERGE_ZERO, enumerator
H A DAArch64ISelLowering.cpp2149 MAKE_CASE(AArch64ISD::GLD1_UXTW_MERGE_ZERO) in getTargetNodeName()
4256 AArch64ISD::GLD1_UXTW_MERGE_ZERO}, in getGatherVecOpcode()
4306 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in getSignExtendedGatherOpcode()
13474 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSVEAndCombine()
15343 Opc == AArch64ISD::GLD1_UXTW_MERGE_ZERO || in performGLD1Combine()
16583 ? AArch64ISD::GLD1_UXTW_MERGE_ZERO in performGatherLoadCombine()
16706 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in performSignExtendInRegCombine()
16975 case AArch64ISD::GLD1_UXTW_MERGE_ZERO: in PerformDAGCombine()
17081 return performGatherLoadCombine(N, DAG, AArch64ISD::GLD1_UXTW_MERGE_ZERO, in PerformDAGCombine()

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