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Searched refs:GPIO2_BASE (Results 1 – 25 of 225) sorted by relevance

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/dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c226 val = mmio_read_32(GPIO2_BASE + SWPORTA_DDR); in rockchip_soc_system_off()
228 mmio_write_32(GPIO2_BASE + SWPORTA_DDR, val); in rockchip_soc_system_off()
231 val = mmio_read_32(GPIO2_BASE); in rockchip_soc_system_off()
233 mmio_write_32(GPIO2_BASE, val); in rockchip_soc_system_off()
472 sram_data.pmic_sleep_gpio_save[1] = mmio_read_32(GPIO2_BASE + 4); in rk3328_pmic_suspend()
473 sram_data.pmic_sleep_gpio_save[0] = mmio_read_32(GPIO2_BASE); in rk3328_pmic_suspend()
475 mmio_write_32(GPIO2_BASE + 4, in rk3328_pmic_suspend()
477 mmio_write_32(GPIO2_BASE, in rk3328_pmic_suspend()
483 mmio_write_32(GPIO2_BASE, sram_data.pmic_sleep_gpio_save[0]); in rk3328_pmic_resume()
484 mmio_write_32(GPIO2_BASE + 4, sram_data.pmic_sleep_gpio_save[1]); in rk3328_pmic_resume()
/dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c226 val = mmio_read_32(GPIO2_BASE + SWPORTA_DDR); in rockchip_soc_system_off()
228 mmio_write_32(GPIO2_BASE + SWPORTA_DDR, val); in rockchip_soc_system_off()
231 val = mmio_read_32(GPIO2_BASE); in rockchip_soc_system_off()
233 mmio_write_32(GPIO2_BASE, val); in rockchip_soc_system_off()
472 sram_data.pmic_sleep_gpio_save[1] = mmio_read_32(GPIO2_BASE + 4); in rk3328_pmic_suspend()
473 sram_data.pmic_sleep_gpio_save[0] = mmio_read_32(GPIO2_BASE); in rk3328_pmic_suspend()
475 mmio_write_32(GPIO2_BASE + 4, in rk3328_pmic_suspend()
477 mmio_write_32(GPIO2_BASE, in rk3328_pmic_suspend()
483 mmio_write_32(GPIO2_BASE, sram_data.pmic_sleep_gpio_save[0]); in rk3328_pmic_resume()
484 mmio_write_32(GPIO2_BASE + 4, sram_data.pmic_sleep_gpio_save[1]); in rk3328_pmic_resume()
/dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c226 val = mmio_read_32(GPIO2_BASE + SWPORTA_DDR); in rockchip_soc_system_off()
228 mmio_write_32(GPIO2_BASE + SWPORTA_DDR, val); in rockchip_soc_system_off()
231 val = mmio_read_32(GPIO2_BASE); in rockchip_soc_system_off()
233 mmio_write_32(GPIO2_BASE, val); in rockchip_soc_system_off()
472 sram_data.pmic_sleep_gpio_save[1] = mmio_read_32(GPIO2_BASE + 4); in rk3328_pmic_suspend()
473 sram_data.pmic_sleep_gpio_save[0] = mmio_read_32(GPIO2_BASE); in rk3328_pmic_suspend()
475 mmio_write_32(GPIO2_BASE + 4, in rk3328_pmic_suspend()
477 mmio_write_32(GPIO2_BASE, in rk3328_pmic_suspend()
483 mmio_write_32(GPIO2_BASE, sram_data.pmic_sleep_gpio_save[0]); in rk3328_pmic_resume()
484 mmio_write_32(GPIO2_BASE + 4, sram_data.pmic_sleep_gpio_save[1]); in rk3328_pmic_resume()
/dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c226 val = mmio_read_32(GPIO2_BASE + SWPORTA_DDR); in rockchip_soc_system_off()
228 mmio_write_32(GPIO2_BASE + SWPORTA_DDR, val); in rockchip_soc_system_off()
231 val = mmio_read_32(GPIO2_BASE); in rockchip_soc_system_off()
233 mmio_write_32(GPIO2_BASE, val); in rockchip_soc_system_off()
472 sram_data.pmic_sleep_gpio_save[1] = mmio_read_32(GPIO2_BASE + 4); in rk3328_pmic_suspend()
473 sram_data.pmic_sleep_gpio_save[0] = mmio_read_32(GPIO2_BASE); in rk3328_pmic_suspend()
475 mmio_write_32(GPIO2_BASE + 4, in rk3328_pmic_suspend()
477 mmio_write_32(GPIO2_BASE, in rk3328_pmic_suspend()
483 mmio_write_32(GPIO2_BASE, sram_data.pmic_sleep_gpio_save[0]); in rk3328_pmic_resume()
484 mmio_write_32(GPIO2_BASE + 4, sram_data.pmic_sleep_gpio_save[1]); in rk3328_pmic_resume()
/dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c226 val = mmio_read_32(GPIO2_BASE + SWPORTA_DDR); in rockchip_soc_system_off()
228 mmio_write_32(GPIO2_BASE + SWPORTA_DDR, val); in rockchip_soc_system_off()
231 val = mmio_read_32(GPIO2_BASE); in rockchip_soc_system_off()
233 mmio_write_32(GPIO2_BASE, val); in rockchip_soc_system_off()
472 sram_data.pmic_sleep_gpio_save[1] = mmio_read_32(GPIO2_BASE + 4); in rk3328_pmic_suspend()
473 sram_data.pmic_sleep_gpio_save[0] = mmio_read_32(GPIO2_BASE); in rk3328_pmic_suspend()
475 mmio_write_32(GPIO2_BASE + 4, in rk3328_pmic_suspend()
477 mmio_write_32(GPIO2_BASE, in rk3328_pmic_suspend()
483 mmio_write_32(GPIO2_BASE, sram_data.pmic_sleep_gpio_save[0]); in rk3328_pmic_resume()
484 mmio_write_32(GPIO2_BASE + 4, sram_data.pmic_sleep_gpio_save[1]); in rk3328_pmic_resume()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/mips/include/asm/
H A Dau1x00.h903 #define GPIO2_BASE 0xB1700000 macro
904 #define GPIO2_DIR (GPIO2_BASE + 0)
905 #define GPIO2_DATA_EN (GPIO2_BASE + 8)
906 #define GPIO2_PIN_STATE (GPIO2_BASE + 0xC)
907 #define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10)
908 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/mips/include/asm/
H A Dau1x00.h903 #define GPIO2_BASE 0xB1700000 macro
904 #define GPIO2_DIR (GPIO2_BASE + 0)
905 #define GPIO2_DATA_EN (GPIO2_BASE + 8)
906 #define GPIO2_PIN_STATE (GPIO2_BASE + 0xC)
907 #define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10)
908 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/mips/include/asm/
H A Dau1x00.h903 #define GPIO2_BASE 0xB1700000 macro
904 #define GPIO2_DIR (GPIO2_BASE + 0)
905 #define GPIO2_DATA_EN (GPIO2_BASE + 8)
906 #define GPIO2_PIN_STATE (GPIO2_BASE + 0xC)
907 #define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10)
908 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/mips/include/asm/
H A Dau1x00.h903 #define GPIO2_BASE 0xB1700000 macro
904 #define GPIO2_DIR (GPIO2_BASE + 0)
905 #define GPIO2_DATA_EN (GPIO2_BASE + 8)
906 #define GPIO2_PIN_STATE (GPIO2_BASE + 0xC)
907 #define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10)
908 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/mips/include/asm/
H A Dau1x00.h903 #define GPIO2_BASE 0xB1700000 macro
904 #define GPIO2_DIR (GPIO2_BASE + 0)
905 #define GPIO2_DATA_EN (GPIO2_BASE + 8)
906 #define GPIO2_PIN_STATE (GPIO2_BASE + 0xC)
907 #define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10)
908 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/mips/include/asm/
H A Dau1x00.h903 #define GPIO2_BASE 0xB1700000 macro
904 #define GPIO2_DIR (GPIO2_BASE + 0)
905 #define GPIO2_DATA_EN (GPIO2_BASE + 8)
906 #define GPIO2_PIN_STATE (GPIO2_BASE + 0xC)
907 #define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10)
908 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/mips/include/asm/
H A Dau1x00.h885 #define GPIO2_BASE 0xB1700000 macro
886 #define GPIO2_DIR (GPIO2_BASE + 0)
887 #define GPIO2_DATA_EN (GPIO2_BASE + 8)
888 #define GPIO2_PIN_STATE (GPIO2_BASE + 0xC)
889 #define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10)
890 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/mips/include/asm/
H A Dau1x00.h903 #define GPIO2_BASE 0xB1700000 macro
904 #define GPIO2_DIR (GPIO2_BASE + 0)
905 #define GPIO2_DATA_EN (GPIO2_BASE + 8)
906 #define GPIO2_PIN_STATE (GPIO2_BASE + 0xC)
907 #define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10)
908 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/board/micronas/vct/vctv/
H A Dreg_gpio.h7 #define GPIO2_BASE 0x00048000 macro
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/board/micronas/vct/vcth/
H A Dreg_gpio.h7 #define GPIO2_BASE 0x0008c000 macro
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/board/micronas/vct/vctv/
H A Dreg_gpio.h7 #define GPIO2_BASE 0x00048000 macro
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/board/micronas/vct/vcth/
H A Dreg_gpio.h7 #define GPIO2_BASE 0x0008c000 macro
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/board/micronas/vct/vctv/
H A Dreg_gpio.h7 #define GPIO2_BASE 0x00048000 macro
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/board/micronas/vct/vcth/
H A Dreg_gpio.h7 #define GPIO2_BASE 0x0008c000 macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/board/micronas/vct/vcth/
H A Dreg_gpio.h7 #define GPIO2_BASE 0x0008c000 macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/board/micronas/vct/vctv/
H A Dreg_gpio.h7 #define GPIO2_BASE 0x00048000 macro
/dports/sysutils/u-boot-utilite/u-boot-2015.07/board/micronas/vct/vcth/
H A Dreg_gpio.h8 #define GPIO2_BASE 0x0008c000 macro
/dports/sysutils/u-boot-utilite/u-boot-2015.07/board/micronas/vct/vctv/
H A Dreg_gpio.h8 #define GPIO2_BASE 0x00048000 macro
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/board/micronas/vct/vctv/
H A Dreg_gpio.h7 #define GPIO2_BASE 0x00048000 macro
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/board/micronas/vct/vcth/
H A Dreg_gpio.h7 #define GPIO2_BASE 0x0008c000 macro

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