/dports/emulators/qemu60/qemu-6.0.0/roms/edk2/ArmPlatformPkg/Drivers/PL061GpioDxe/ |
H A D | PL061Gpio.c | 184 if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset))) { in Get() 230 ~GPIO_PIN_MASK(Offset) & 0xFF); in Set() 235 MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset)); in Set() 237 PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0); in Set() 242 MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset)); in Set() 244 PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0xff); in Set() 293 if (MmioRead8 (RegisterBase + PL061_GPIO_DIR_REG) & GPIO_PIN_MASK(Offset)) { in GetMode() 295 if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset))) { in GetMode()
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H A D | PL061Gpio.h | 41 #define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin))) macro
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/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/ArmPlatformPkg/Drivers/PL061GpioDxe/ |
H A D | PL061Gpio.c | 184 if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset))) { in Get() 230 ~GPIO_PIN_MASK(Offset) & 0xFF); in Set() 235 MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset)); in Set() 237 PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0); in Set() 242 MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset)); in Set() 244 PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0xff); in Set() 293 if (MmioRead8 (RegisterBase + PL061_GPIO_DIR_REG) & GPIO_PIN_MASK(Offset)) { in GetMode() 295 if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset))) { in GetMode()
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H A D | PL061Gpio.h | 41 #define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin))) macro
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/dports/emulators/qemu/qemu-6.2.0/roms/edk2/ArmPlatformPkg/Drivers/PL061GpioDxe/ |
H A D | PL061Gpio.c | 184 if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset))) { in Get() 230 ~GPIO_PIN_MASK(Offset) & 0xFF); in Set() 235 MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset)); in Set() 237 PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0); in Set() 242 MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset)); in Set() 244 PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0xff); in Set() 293 if (MmioRead8 (RegisterBase + PL061_GPIO_DIR_REG) & GPIO_PIN_MASK(Offset)) { in GetMode() 295 if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset))) { in GetMode()
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H A D | PL061Gpio.h | 41 #define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin))) macro
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/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/ArmPlatformPkg/Drivers/PL061GpioDxe/ |
H A D | PL061Gpio.c | 184 if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset))) { in Get() 230 ~GPIO_PIN_MASK(Offset) & 0xFF); in Set() 235 MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset)); in Set() 237 PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0); in Set() 242 MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset)); in Set() 244 PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0xff); in Set() 293 if (MmioRead8 (RegisterBase + PL061_GPIO_DIR_REG) & GPIO_PIN_MASK(Offset)) { in GetMode() 295 if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset))) { in GetMode()
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H A D | PL061Gpio.h | 41 #define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin))) macro
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/ArmPlatformPkg/Drivers/PL061GpioDxe/ |
H A D | PL061Gpio.c | 184 if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset))) { in Get() 230 ~GPIO_PIN_MASK(Offset) & 0xFF); in Set() 235 MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset)); in Set() 237 PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0); in Set() 242 MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset)); in Set() 244 PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0xff); in Set() 293 if (MmioRead8 (RegisterBase + PL061_GPIO_DIR_REG) & GPIO_PIN_MASK(Offset)) { in GetMode() 295 if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset))) { in GetMode()
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H A D | PL061Gpio.h | 41 #define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin))) macro
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/dports/emulators/qemu5/qemu-5.2.0/roms/edk2/ArmPlatformPkg/Drivers/PL061GpioDxe/ |
H A D | PL061Gpio.c | 184 if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset))) { in Get() 230 ~GPIO_PIN_MASK(Offset) & 0xFF); in Set() 235 MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset)); in Set() 237 PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0); in Set() 242 MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset)); in Set() 244 PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0xff); in Set() 293 if (MmioRead8 (RegisterBase + PL061_GPIO_DIR_REG) & GPIO_PIN_MASK(Offset)) { in GetMode() 295 if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset))) { in GetMode()
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H A D | PL061Gpio.h | 41 #define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin))) macro
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/dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/ArmPlatformPkg/Drivers/PL061GpioDxe/ |
H A D | PL061Gpio.c | 184 if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset)) != 0) { in Get() 230 ~GPIO_PIN_MASK(Offset) & 0xFF); in Set() 235 MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset)); in Set() 237 PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0); in Set() 242 MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset)); in Set() 244 PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0xff); in Set() 293 if (MmioRead8 (RegisterBase + PL061_GPIO_DIR_REG) & GPIO_PIN_MASK(Offset)) { in GetMode() 295 if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset)) != 0) { in GetMode()
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H A D | PL061Gpio.h | 41 #define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin))) macro
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/ArmPlatformPkg/Drivers/PL061GpioDxe/ |
H A D | PL061Gpio.c | 184 if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset))) { 230 ~GPIO_PIN_MASK(Offset) & 0xFF); 235 MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset)); 237 PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0); 242 MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset)); 244 PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0xff); 293 if (MmioRead8 (RegisterBase + PL061_GPIO_DIR_REG) & GPIO_PIN_MASK(Offset)) { 295 if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset))) {
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H A D | PL061Gpio.h | 41 #define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin)))
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/dports/sysutils/edk2/edk2-edk2-stable202102/ArmPlatformPkg/Drivers/PL061GpioDxe/ |
H A D | PL061Gpio.c | 184 if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset)) != 0) { in Get() 230 ~GPIO_PIN_MASK(Offset) & 0xFF); in Set() 235 MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset)); in Set() 237 PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0); in Set() 242 MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset)); in Set() 244 PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0xff); in Set() 293 if (MmioRead8 (RegisterBase + PL061_GPIO_DIR_REG) & GPIO_PIN_MASK(Offset)) { in GetMode() 295 if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset)) != 0) { in GetMode()
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H A D | PL061Gpio.h | 41 #define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin))) macro
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/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/ArmPlatformPkg/Include/Drivers/ |
H A D | PL061Gpio.h | 48 #define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin))) macro 50 #define GPIO_PIN_MASK_HIGH_8BIT(Pin) (GPIO_PIN_MASK(Pin) && 0xFF) 52 #define GPIO_PIN_MASK_LOW_8BIT(Pin) ((~GPIO_PIN_MASK(Pin)) && 0xFF)
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32G4xx_HAL_Driver/inc/ |
H A D | stm32g4xx_hal_gpio.h | 103 #define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */ macro 216 #define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ 217 (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32H7xx_HAL_Driver/inc/ |
H A D | stm32h7xx_hal_gpio.h | 104 #define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */ macro 299 #define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ 300 (((__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
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/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/ |
H A D | stm32l1xx_hal_gpio.h | 124 #define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ macro 204 #define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\ 205 (((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00))
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/dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/ |
H A D | stm32l1xx_hal_gpio.h | 124 #define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ macro 204 #define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\ 205 (((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00))
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/dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/ |
H A D | stm32l1xx_hal_gpio.h | 124 #define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ macro 204 #define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\ 205 (((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00))
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/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/ |
H A D | stm32l1xx_hal_gpio.h | 124 #define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ 204 #define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\ 205 (((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00))
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