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Searched refs:GPKCON0_OFFSET (Results 1 – 7 of 7) sorted by relevance

/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/arm/include/asm/arch-s3c64xx/
H A Ds3c6400.h261 #define GPKCON0_OFFSET 0x800 macro
344 #define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET)
435 #define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET)
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/arm/include/asm/arch-s3c64xx/
H A Ds3c6400.h261 #define GPKCON0_OFFSET 0x800 macro
344 #define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET)
435 #define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/arm/include/asm/arch-s3c64xx/
H A Ds3c6400.h261 #define GPKCON0_OFFSET 0x800 macro
344 #define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET)
435 #define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET)
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/arm/include/asm/arch-s3c64xx/
H A Ds3c6400.h261 #define GPKCON0_OFFSET 0x800 macro
344 #define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET)
435 #define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET)
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/arm/include/asm/arch-s3c64xx/
H A Ds3c6400.h261 #define GPKCON0_OFFSET 0x800 macro
344 #define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET)
435 #define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET)
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/arm/include/asm/arch-s3c64xx/
H A Ds3c6400.h261 #define GPKCON0_OFFSET 0x800 macro
344 #define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET)
435 #define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET)
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/arm/include/asm/arch-s3c64xx/
H A Ds3c6400.h261 #define GPKCON0_OFFSET 0x800 macro
344 #define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET)
435 #define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET)