| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 42 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
119 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
120 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
122 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
123 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
125 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
126 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
142 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
143 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 42 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
119 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
120 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
122 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
123 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
125 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
126 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
142 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
143 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 42 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
119 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
120 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
122 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
123 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
125 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
126 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
142 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
143 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
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| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
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| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 42 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
119 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
120 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
122 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
123 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
125 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
126 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
142 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
143 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
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| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
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