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Searched refs:GPRArgRegs (Results 1 – 25 of 69) sorted by relevance

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/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AArch64/
H A DAArch64RegisterInfo.cpp221 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
224 return std::any_of(std::begin(GPRArgRegs), std::end(GPRArgRegs),
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/ARM/
H A DARMCallingConv.cpp70 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS() local
76 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
H A DARMFastISel.cpp3055 static const MCPhysReg GPRArgRegs[] = { in fastLowerArguments() local
3062 unsigned SrcReg = GPRArgRegs[ArgNo]; in fastLowerArguments()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp70 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS() local
76 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp70 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS() local
76 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
H A DARMFastISel.cpp3055 static const MCPhysReg GPRArgRegs[] = { in fastLowerArguments() local
3062 unsigned SrcReg = GPRArgRegs[ArgNo]; in fastLowerArguments()
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/ARM/
H A DARMCallingConv.cpp70 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS() local
76 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/ARM/
H A DARMCallingConv.h77 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS() local
83 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/ARM/
H A DARMCallingConv.h77 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS() local
83 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS() local
74 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
H A DARMFastISel.cpp3049 static const MCPhysReg GPRArgRegs[] = { in fastLowerArguments() local
3056 unsigned SrcReg = GPRArgRegs[ArgNo]; in fastLowerArguments()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS() local
74 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
H A DARMFastISel.cpp3049 static const MCPhysReg GPRArgRegs[] = { in fastLowerArguments() local
3056 unsigned SrcReg = GPRArgRegs[ArgNo]; in fastLowerArguments()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
74 Reg = State.AllocateReg(GPRArgRegs);
H A DARMFastISel.cpp3052 static const MCPhysReg GPRArgRegs[] = {
3059 unsigned SrcReg = GPRArgRegs[ArgNo];
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/
H A DARMCallingConv.cpp68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS() local
74 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
H A DARMFastISel.cpp3052 static const MCPhysReg GPRArgRegs[] = { in fastLowerArguments() local
3059 unsigned SrcReg = GPRArgRegs[ArgNo]; in fastLowerArguments()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS() local
74 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
H A DARMFastISel.cpp3055 static const MCPhysReg GPRArgRegs[] = { in fastLowerArguments() local
3062 unsigned SrcReg = GPRArgRegs[ArgNo]; in fastLowerArguments()
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/
H A DARMCallingConv.cpp68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS() local
74 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS() local
74 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS() local
74 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS() local
74 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS() local
74 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS() local
74 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()

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