1 //***************************************************************************** 2 // 3 // Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 4 // 5 // 6 // Redistribution and use in source and binary forms, with or without 7 // modification, are permitted provided that the following conditions 8 // are met: 9 // 10 // Redistributions of source code must retain the above copyright 11 // notice, this list of conditions and the following disclaimer. 12 // 13 // Redistributions in binary form must reproduce the above copyright 14 // notice, this list of conditions and the following disclaimer in the 15 // documentation and/or other materials provided with the 16 // distribution. 17 // 18 // Neither the name of Texas Instruments Incorporated nor the names of 19 // its contributors may be used to endorse or promote products derived 20 // from this software without specific prior written permission. 21 // 22 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 26 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 28 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 // 34 //***************************************************************************** 35 36 #ifndef __HW_HIB3P3_H__ 37 #define __HW_HIB3P3_H__ 38 39 //***************************************************************************** 40 // 41 // The following are defines for the HIB3P3 register offsets. 42 // 43 //***************************************************************************** 44 #define HIB3P3_O_MEM_HIB_REQ 0x00000000 45 #define HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE \ 46 0x00000004 47 48 #define HIB3P3_O_MEM_HIB_RTC_TIMER_RESET \ 49 0x00000008 50 51 #define HIB3P3_O_MEM_HIB_RTC_TIMER_READ \ 52 0x0000000C 53 54 #define HIB3P3_O_MEM_HIB_RTC_TIMER_LSW \ 55 0x00000010 56 57 #define HIB3P3_O_MEM_HIB_RTC_TIMER_MSW \ 58 0x00000014 59 60 #define HIB3P3_O_MEM_HIB_RTC_WAKE_EN \ 61 0x00000018 62 63 #define HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF \ 64 0x0000001C 65 66 #define HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF \ 67 0x00000020 68 69 #define HIB3P3_O_MEM_INT_OSC_CONF \ 70 0x0000002C 71 72 #define HIB3P3_O_MEM_XTAL_OSC_CONF \ 73 0x00000034 74 75 #define HIB3P3_O_MEM_BGAP_PARAMETERS0 \ 76 0x00000038 77 78 #define HIB3P3_O_MEM_BGAP_PARAMETERS1 \ 79 0x0000003C 80 81 #define HIB3P3_O_MEM_HIB_DETECTION_STATUS \ 82 0x00000040 83 84 #define HIB3P3_O_MEM_HIB_MISC_CONTROLS \ 85 0x00000044 86 87 #define HIB3P3_O_MEM_HIB_CONFIG 0x00000050 88 #define HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE \ 89 0x00000054 90 91 #define HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF \ 92 0x00000058 93 94 #define HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF \ 95 0x0000005C 96 97 #define HIB3P3_O_MEM_HIB_UART_CONF \ 98 0x00000400 99 100 #define HIB3P3_O_MEM_GPIO_WAKE_EN \ 101 0x00000404 102 103 #define HIB3P3_O_MEM_GPIO_WAKE_CONF \ 104 0x00000408 105 106 #define HIB3P3_O_MEM_PAD_OEN_RET33_CONF \ 107 0x0000040C 108 109 #define HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF \ 110 0x00000410 111 112 #define HIB3P3_O_MEM_JTAG_CONF 0x00000414 113 #define HIB3P3_O_MEM_HIB_REG0 0x00000418 114 #define HIB3P3_O_MEM_HIB_REG1 0x0000041C 115 #define HIB3P3_O_MEM_HIB_REG2 0x00000420 116 #define HIB3P3_O_MEM_HIB_REG3 0x00000424 117 #define HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 \ 118 0x0000045C 119 120 #define HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 \ 121 0x00000460 122 123 #define HIB3P3_O_MEM_HIB_MISC_CONFIG \ 124 0x00000464 125 126 #define HIB3P3_O_MEM_HIB_WAKE_STATUS \ 127 0x00000468 128 129 #define HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL \ 130 0x0000046C 131 132 #define HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 \ 133 0x00000470 134 135 #define HIB3P3_O_HIBANA_SPARE_LOWV \ 136 0x00000474 137 138 #define HIB3P3_O_HIB_TMUX_CTRL 0x00000478 139 #define HIB3P3_O_HIB_1P2_1P8_LDO_TRIM \ 140 0x0000047C 141 142 #define HIB3P3_O_HIB_COMP_TRIM 0x00000480 143 #define HIB3P3_O_HIB_EN_TS 0x00000484 144 #define HIB3P3_O_HIB_1P8V_DET_EN \ 145 0x00000488 146 147 #define HIB3P3_O_HIB_VBAT_MON_EN \ 148 0x0000048C 149 150 #define HIB3P3_O_HIB_NHIB_ENABLE \ 151 0x00000490 152 153 #define HIB3P3_O_HIB_UART_RTS_SW_ENABLE \ 154 0x00000494 155 156 157 158 159 //****************************************************************************** 160 // 161 // The following are defines for the bit fields in the 162 // HIB3P3_O_MEM_HIB_REQ register. 163 // 164 //****************************************************************************** 165 #define HIB3P3_MEM_HIB_REQ_reserved_M \ 166 0xFFFFFE00 167 168 #define HIB3P3_MEM_HIB_REQ_reserved_S 9 169 #define HIB3P3_MEM_HIB_REQ_NU1_M \ 170 0x000001FC 171 172 #define HIB3P3_MEM_HIB_REQ_NU1_S 2 173 #define HIB3P3_MEM_HIB_REQ_mem_hib_clk_disable \ 174 0x00000002 // 1 - Specifies that the Hiberante 175 // mode is without clocks ; 0 - 176 // Specified that the Hibernate mode 177 // is with clocks This register will 178 // be reset during Hibernate 179 // -WO-Clks mode (but not during 180 // Hibernate-W-Clks mode). 181 182 #define HIB3P3_MEM_HIB_REQ_mem_hib_req \ 183 0x00000001 // 1 - Request for hibernate mode 184 // (This is an auto-clear bit) ; 0 - 185 // Donot request for hibernate mode 186 // This register will be reset 187 // during Hibernate -WO-Clks mode 188 // (but not during Hibernate-W-Clks 189 // mode). 190 191 //****************************************************************************** 192 // 193 // The following are defines for the bit fields in the 194 // HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE register. 195 // 196 //****************************************************************************** 197 #define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_M \ 198 0xFFFFFFFE 199 200 #define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_S 1 201 #define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_mem_hib_rtc_timer_enable \ 202 0x00000001 // 1 - Enable the RTC timer to 203 // start running ; 0 - Keep the RTC 204 // timer disabled This register will 205 // be reset during Hibernate 206 // -WO-Clks mode (but not during 207 // Hibernate-W-Clks mode). 208 209 //****************************************************************************** 210 // 211 // The following are defines for the bit fields in the 212 // HIB3P3_O_MEM_HIB_RTC_TIMER_RESET register. 213 // 214 //****************************************************************************** 215 #define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_M \ 216 0xFFFFFFFE 217 218 #define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_S 1 219 #define HIB3P3_MEM_HIB_RTC_TIMER_RESET_mem_hib_rtc_timer_reset \ 220 0x00000001 // 1 - Reset the RTC timer ; 0 - 221 // Donot reset the RTC timer. This 222 // is an auto-clear bit. This 223 // register will be reset during 224 // Hibernate -WO-Clks mode (but not 225 // during Hibernate-W-Clks mode). 226 227 //****************************************************************************** 228 // 229 // The following are defines for the bit fields in the 230 // HIB3P3_O_MEM_HIB_RTC_TIMER_READ register. 231 // 232 //****************************************************************************** 233 #define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_M \ 234 0xFFFFFFFE 235 236 #define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_S 1 237 #define HIB3P3_MEM_HIB_RTC_TIMER_READ_mem_hib_rtc_timer_read \ 238 0x00000001 // 1 - Latch the running RTC timer 239 // into local registers. After 240 // programming this bit to 1, the 241 // F/w can read the latched RTC 242 // timer values from 243 // MEM_HIB_RTC_TIMER_LSW and 244 // MEM_HIB_RTC_TIMER_MSW. Before the 245 // F/w (APPS or NWP) wants to read 246 // the RTC-Timer, it has to program 247 // this bit to 1, then only read the 248 // MSW and LSW values. This is an 249 // auto-clear bit. This register 250 // will be reset during Hibernate 251 // -WO-Clks mode (but not during 252 // Hibernate-W-Clks mode). 253 254 //****************************************************************************** 255 // 256 // The following are defines for the bit fields in the 257 // HIB3P3_O_MEM_HIB_RTC_TIMER_LSW register. 258 // 259 //****************************************************************************** 260 #define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_M \ 261 0xFFFFFFFF // Lower 32b value of the latched 262 // RTC-Timer. 263 264 #define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_S 0 265 //****************************************************************************** 266 // 267 // The following are defines for the bit fields in the 268 // HIB3P3_O_MEM_HIB_RTC_TIMER_MSW register. 269 // 270 //****************************************************************************** 271 #define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_M \ 272 0xFFFF0000 273 274 #define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_S 16 275 #define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_M \ 276 0x0000FFFF // Upper 32b value of the latched 277 // RTC-Timer. 278 279 #define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_S 0 280 //****************************************************************************** 281 // 282 // The following are defines for the bit fields in the 283 // HIB3P3_O_MEM_HIB_RTC_WAKE_EN register. 284 // 285 //****************************************************************************** 286 #define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_M \ 287 0xFFFFFFFE 288 289 #define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_S 1 290 #define HIB3P3_MEM_HIB_RTC_WAKE_EN_mem_hib_rtc_wake_en \ 291 0x00000001 // 1 - Enable the RTC timer based 292 // wakeup during Hibernate mode ; 0 293 // - Disable the RTC timer based 294 // wakeup during Hibernate mode This 295 // register will be reset during 296 // Hibernate-WO-Clks mode (but not 297 // during Hibernate-W-Clks mode). 298 299 //****************************************************************************** 300 // 301 // The following are defines for the bit fields in the 302 // HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF register. 303 // 304 //****************************************************************************** 305 #define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_M \ 306 0xFFFFFFFF // Configuration for RTC-Timer 307 // Wakeup (Lower 32b word) 308 309 #define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_S 0 310 //****************************************************************************** 311 // 312 // The following are defines for the bit fields in the 313 // HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF register. 314 // 315 //****************************************************************************** 316 #define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_M \ 317 0xFFFF0000 318 319 #define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_S 16 320 #define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_M \ 321 0x0000FFFF // Configuration for RTC-Timer 322 // Wakeup (Upper 16b word) 323 324 #define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_S 0 325 //****************************************************************************** 326 // 327 // The following are defines for the bit fields in the 328 // HIB3P3_O_MEM_INT_OSC_CONF register. 329 // 330 //****************************************************************************** 331 #define HIB3P3_MEM_INT_OSC_CONF_reserved_M \ 332 0xFFFF0000 333 334 #define HIB3P3_MEM_INT_OSC_CONF_reserved_S 16 335 #define HIB3P3_MEM_INT_OSC_CONF_cm_clk_good_32k_int \ 336 0x00008000 // 1 - Internal 32kHz Oscillator is 337 // valid ; 0 - Internal 32k 338 // oscillator clk is not valid 339 340 #define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_M \ 341 0x00007E00 342 343 #define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_S 9 344 #define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k_override_ctrl \ 345 0x00000100 // When 1, the INT_32K_OSC_EN comes 346 // from bit [0] of this register, 347 // else comes from the FSM. This 348 // register will be reset during 349 // Hibernate-WO-Clks mode (but not 350 // during Hibernate-W-Clks mode) 351 352 #define HIB3P3_MEM_INT_OSC_CONF_NU1 \ 353 0x00000080 354 355 #define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_M \ 356 0x0000007E 357 358 #define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_S 1 359 #define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k \ 360 0x00000001 // Override value for INT_OSC_EN. 361 // Applicable only when bit [3] of 362 // this register is set to 1. 363 364 //****************************************************************************** 365 // 366 // The following are defines for the bit fields in the 367 // HIB3P3_O_MEM_XTAL_OSC_CONF register. 368 // 369 //****************************************************************************** 370 #define HIB3P3_MEM_XTAL_OSC_CONF_reserved_M \ 371 0xFFF00000 372 373 #define HIB3P3_MEM_XTAL_OSC_CONF_reserved_S 20 374 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k_override_ctrl \ 375 0x00080000 // When 1, the SLICER_EN comes from 376 // bit [10] of this register, else 377 // comes from the FSM. 378 379 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k_override_ctrl \ 380 0x00040000 // When 1, the XTAL_EN comes from 381 // bit [0] of this register, else 382 // comes from the FSM. 383 384 #define HIB3P3_MEM_XTAL_OSC_CONF_cm_clk_good_xtal \ 385 0x00020000 // 1 - XTAL Clk is good ; 0 - XTAL 386 // Clk is yet to be valid. 387 388 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_M \ 389 0x0001F800 390 391 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_S 11 392 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k \ 393 0x00000400 // SLICER_EN Override value : 394 // Applicable only when bit [19] of 395 // this register is set to 1. 396 397 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_M \ 398 0x00000380 399 400 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_S 7 401 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_M \ 402 0x00000070 403 404 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_S 4 405 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_fref_32k_slicer \ 406 0x00000008 407 408 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_M \ 409 0x00000006 410 411 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_S 1 412 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k \ 413 0x00000001 // XTAL_EN Override value : 414 // Applicable only when bit [18] of 415 // this register is set to 1. 416 417 //****************************************************************************** 418 // 419 // The following are defines for the bit fields in the 420 // HIB3P3_O_MEM_BGAP_PARAMETERS0 register. 421 // 422 //****************************************************************************** 423 #define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_M \ 424 0xFFF80000 425 426 #define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_S 19 427 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_en_seq \ 428 0x00040000 429 430 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_M \ 431 0x0001C000 432 433 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_S 14 434 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbat_ok_4bg \ 435 0x00001000 436 437 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp \ 438 0x00000800 439 440 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp_ref \ 441 0x00000400 442 443 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_M \ 444 0x000003FF 445 446 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_S 0 447 //****************************************************************************** 448 // 449 // The following are defines for the bit fields in the 450 // HIB3P3_O_MEM_BGAP_PARAMETERS1 register. 451 // 452 //****************************************************************************** 453 #define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_M \ 454 0xE0000000 455 456 #define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_S 29 457 #define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_M \ 458 0x1F000000 459 460 #define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_S 24 461 #define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_act_iref \ 462 0x00000008 463 464 #define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_v2i \ 465 0x00000004 466 467 #define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_cap_sw \ 468 0x00000002 469 470 #define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en \ 471 0x00000001 472 473 //****************************************************************************** 474 // 475 // The following are defines for the bit fields in the 476 // HIB3P3_O_MEM_HIB_DETECTION_STATUS register. 477 // 478 //****************************************************************************** 479 #define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_M \ 480 0xFFFFFF80 481 482 #define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_S 7 483 #define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_ana_status \ 484 0x00000040 // 1 - 1.8 V supply forced mode. 485 486 #define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_flash_status \ 487 0x00000004 // 1 - 3.3 V supply forced mode for 488 // Flash supply 489 490 #define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_ext_clk_det_out_status \ 491 0x00000002 // 1 - Forced clock mode 492 493 #define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_xtal_det_out_status \ 494 0x00000001 // 1 - XTAL clock mode 495 496 //****************************************************************************** 497 // 498 // The following are defines for the bit fields in the 499 // HIB3P3_O_MEM_HIB_MISC_CONTROLS register. 500 // 501 //****************************************************************************** 502 #define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_M \ 503 0xFFFFF800 504 505 #define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_S 11 506 #define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp \ 507 0x00000400 508 509 #define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp_ref \ 510 0x00000200 511 512 #define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_M \ 513 0x000001C0 514 515 #define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_S 6 516 #define HIB3P3_MEM_HIB_MISC_CONTROLS_NU1 \ 517 0x00000020 518 519 #define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_flash_det_en \ 520 0x00000010 521 522 #define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_tmux \ 523 0x00000001 524 525 //****************************************************************************** 526 // 527 // The following are defines for the bit fields in the 528 // HIB3P3_O_MEM_HIB_CONFIG register. 529 // 530 //****************************************************************************** 531 #define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_M \ 532 0xFF000000 533 534 #define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_S 24 535 #define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED3 \ 536 0x00080000 // 1 - Enable VDD_FLASH_INDP_PAD 537 // for digital path (SHARED4) ; 0 - 538 // Disable VDD_FLASH_INDP_PAD for 539 // digital path (SHARED4) ; Before 540 // programming this bit to 1, ensure 541 // that the device is in FORCED 3.3 542 // supply Mode, which can be 543 // inferred from the register : 544 // MEM_HIB_DETECTION_STATUS : 0x0040 545 546 #define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED2 \ 547 0x00040000 // 1 - Enable the 548 // VDD_FB_GPIO_MUX_PAD for digital 549 // path (SHARED3) ; 0 - Disable the 550 // VDD_FB_GPIO_MUX_PAD for digital 551 // path (SHARED3) ; This pin can be 552 // used only in modes other than 553 // SOP("111") 554 555 #define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED1 \ 556 0x00020000 // 1 - Enable the PM_TEST_PAD for 557 // digital GPIO path (SHARED2) ; 0 - 558 // Disable the PM_TEST_PAD for 559 // digital GPIO path (SHARED2) This 560 // pin can be used for digital only 561 // in modes other then SOP-111 562 563 #define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED0 \ 564 0x00010000 // 1 - Enable the XTAL_N pin 565 // digital GPIO path (SHARED1); 0 - 566 // Disable the XTAL_N pin digital 567 // GPIO path (SHARED1). Before 568 // programming this bit to 1, ensure 569 // that the device is in FORCED CLK 570 // Mode, which can inferred from the 571 // register : 572 // MEM_HIB_DETECTION_STATUS : 573 // 0x0040. 574 575 #define HIB3P3_MEM_HIB_CONFIG_mem_hib_xtal_enable \ 576 0x00000100 // 1 - Enable the XTAL Clock ; 0 - 577 // Donot enable the XTAL Clock. This 578 // bit has to be programmed to 1 (by 579 // APPS Devinit F/w), during exit 580 // from OFF or Hib_wo_clks modes, 581 // after checking if the slow_clk 582 // mode is XTAL_CLK mode. Once 583 // enabled the XTAL will be disabled 584 // only after entering HIB_WO_CLKS 585 // mode. This register will be reset 586 // during Hibernate -WO-Clks mode 587 // (but not during Hibernate-W-Clks 588 // mode). 589 590 //****************************************************************************** 591 // 592 // The following are defines for the bit fields in the 593 // HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE register. 594 // 595 //****************************************************************************** 596 #define HIB3P3_MEM_HIB_RTC_IRQ_ENABLE_HIB_RTC_IRQ_ENABLE \ 597 0x00000001 // 1 - Enable the HIB RTC - IRQ ; 0 598 // - Disable the HIB RTC - IRQ 599 600 //****************************************************************************** 601 // 602 // The following are defines for the bit fields in the 603 // HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF register. 604 // 605 //****************************************************************************** 606 #define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_M \ 607 0xFFFFFFFF // Configuration for LSW of the 608 // RTC-Timestamp at which interrupt 609 // need to be generated 610 611 #define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_S 0 612 //****************************************************************************** 613 // 614 // The following are defines for the bit fields in the 615 // HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF register. 616 // 617 //****************************************************************************** 618 #define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_M \ 619 0x0000FFFF // Configuration for MSW of thr 620 // RTC-Timestamp at which the 621 // interrupt need to be generated 622 623 #define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_S 0 624 //****************************************************************************** 625 // 626 // The following are defines for the bit fields in the 627 // HIB3P3_O_MEM_HIB_UART_CONF register. 628 // 629 //****************************************************************************** 630 #define HIB3P3_MEM_HIB_UART_CONF_reserved_M \ 631 0xFFFFFFFE 632 633 #define HIB3P3_MEM_HIB_UART_CONF_reserved_S 1 634 #define HIB3P3_MEM_HIB_UART_CONF_mem_hib_uart_wake_en \ 635 0x00000001 // 1 - Enable the UART-Autonomous 636 // mode wakeup during Hibernate mode 637 // ; This is an auto-clear bit, once 638 // programmed to 1, it will latched 639 // into an internal register which 640 // remain asserted until the 641 // Hib-wakeup is initiated. 642 643 //****************************************************************************** 644 // 645 // The following are defines for the bit fields in the 646 // HIB3P3_O_MEM_GPIO_WAKE_EN register. 647 // 648 //****************************************************************************** 649 #define HIB3P3_MEM_GPIO_WAKE_EN_reserved_M \ 650 0xFFFFFF00 651 652 #define HIB3P3_MEM_GPIO_WAKE_EN_reserved_S 8 653 #define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_M \ 654 0x000000FF // 1 - Enable the GPIO-Autonomous 655 // mode wakeup during Hibernate mode 656 // ; This is an auto-clear bit, once 657 // programmed to 1, it will latched 658 // into an internal register which 659 // remain asserted until the 660 // Hib-wakeup is initiated. 661 662 #define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_S 0 663 //****************************************************************************** 664 // 665 // The following are defines for the bit fields in the 666 // HIB3P3_O_MEM_GPIO_WAKE_CONF register. 667 // 668 //****************************************************************************** 669 #define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_M \ 670 0xFFFF0000 671 672 #define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_S 16 673 #define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_M \ 674 0x0000FFFF // Configuration to say whether the 675 // GPIO wakeup has to happen on 676 // Level0 or falling-edge for the 677 // given group. “00” – Level0 “01” – 678 // Level1 “10”- Fall-edge “11”- 679 // Rise-edge [1:0] – Conf for GPIO0 680 // [3:2] – Conf for GPIO1 [5:4] – 681 // Conf for GPIO2 [7:6] – Conf for 682 // GPIO3 [9:8] – Conf for GPIO4 683 // [11:10] – Conf for GPIO5 [13:12] 684 // – Conf for GPIO6 685 686 #define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_S 0 687 //****************************************************************************** 688 // 689 // The following are defines for the bit fields in the 690 // HIB3P3_O_MEM_PAD_OEN_RET33_CONF register. 691 // 692 //****************************************************************************** 693 #define HIB3P3_MEM_PAD_OEN_RET33_CONF_mem_pad_oen_ret33_override_ctrl \ 694 0x00000004 // 1 - Override the OEN33 and RET33 695 // controls of GPIOs during 696 // SOP-Bootdebug mode ; 0 - Donot 697 // override the OEN33 and RET33 698 // controls of GPIOs during 699 // SOP-Bootdebug mode 700 701 #define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_OEN33_CONF \ 702 0x00000002 703 704 #define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_RET33_CONF \ 705 0x00000001 706 707 //****************************************************************************** 708 // 709 // The following are defines for the bit fields in the 710 // HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF register. 711 // 712 //****************************************************************************** 713 #define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_mem_uart_nrts_oen_ret33_override_ctrl \ 714 0x00000004 // 1 - Override the OEN33 and RET33 715 // controls of UART NRTS GPIO during 716 // SOP-Bootdebug mode ; 0 - Donot 717 // override the OEN33 and RET33 718 // controls of UART NRTS GPIO during 719 // SOP-Bootdebug mode 720 721 #define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_OEN33_CONF \ 722 0x00000002 723 724 #define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_RET33_CONF \ 725 0x00000001 726 727 //****************************************************************************** 728 // 729 // The following are defines for the bit fields in the 730 // HIB3P3_O_MEM_JTAG_CONF register. 731 // 732 //****************************************************************************** 733 #define HIB3P3_MEM_JTAG_CONF_mem_jtag1_oen_ret33_override_ctrl \ 734 0x00000200 735 736 #define HIB3P3_MEM_JTAG_CONF_mem_jtag0_oen_ret33_override_ctrl \ 737 0x00000100 738 739 #define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_OEN33_CONF \ 740 0x00000008 741 742 #define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_RET33_CONF \ 743 0x00000004 744 745 #define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_OEN33_CONF \ 746 0x00000002 747 748 #define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_RET33_CONF \ 749 0x00000001 750 751 //****************************************************************************** 752 // 753 // The following are defines for the bit fields in the 754 // HIB3P3_O_MEM_HIB_REG0 register. 755 // 756 //****************************************************************************** 757 #define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_M \ 758 0xFFFFFFFF 759 760 #define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_S 0 761 //****************************************************************************** 762 // 763 // The following are defines for the bit fields in the 764 // HIB3P3_O_MEM_HIB_REG1 register. 765 // 766 //****************************************************************************** 767 #define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_M \ 768 0xFFFFFFFF 769 770 #define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_S 0 771 //****************************************************************************** 772 // 773 // The following are defines for the bit fields in the 774 // HIB3P3_O_MEM_HIB_REG2 register. 775 // 776 //****************************************************************************** 777 #define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_M \ 778 0xFFFFFFFF 779 780 #define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_S 0 781 //****************************************************************************** 782 // 783 // The following are defines for the bit fields in the 784 // HIB3P3_O_MEM_HIB_REG3 register. 785 // 786 //****************************************************************************** 787 #define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_M \ 788 0xFFFFFFFF 789 790 #define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_S 0 791 //****************************************************************************** 792 // 793 // The following are defines for the bit fields in the 794 // HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 register. 795 // 796 //****************************************************************************** 797 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_M \ 798 0xFFFF0000 // Configuration for the number of 799 // slow-clks between de-assertion of 800 // EN_BG_3P3V to assertion of 801 // EN_BG_3P3V 802 803 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_S 16 804 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_NU1 \ 805 0x00008000 806 807 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_M \ 808 0x00006000 // Configuration for the number of 809 // slow-clks between assertion of 810 // EN_COMP_3P3V and assertion of 811 // EN_COMP_LATCH_3P3V 812 813 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_S 13 814 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_M \ 815 0x00001800 // Configuration for the number of 816 // slow-clks between assertion of 817 // (EN_CAP_SW_3P3V,EN_COMP_REF) and 818 // assertion of (EN_COMP_3P3V) 819 820 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_S 11 821 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_M \ 822 0x00000600 // Configuration for the number of 823 // slow-clks between assertion of 824 // (EN_BG_3P3V) and assertion of 825 // (EN_CAP_SW_3P3V, 826 // EN_COMP_REF_3P3V) 827 828 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_S 9 829 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_crude_ref_comp \ 830 0x00000100 831 832 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_ref_override_ctrl \ 833 0x00000080 // 1 - EN_VBOK4BG_REF comes from 834 // bit[10] of the register 835 // MEM_BGAP_PARAMETERS0 [0x0038]. 0 836 // - EN_VBOK4BG_REF comes directly 837 // from the Hib-Sequencer. 838 839 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_comp_override_ctrl \ 840 0x00000040 // 1 - EN_VBOK4BG comes from 841 // bit[11] of the register 842 // MEM_BGAP_PARAMETERS0 [0x0038]. 0 843 // - EN_VBOK4BG comes directly from 844 // the Hib-Sequencer. 845 846 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_v2i_override_ctrl \ 847 0x00000020 // 1 - EN_V2I comes from bit[2] of 848 // the register MEM_BGAP_PARAMETERS1 849 // [0x003C]. 0 - EN_V2I comes 850 // directly from the Hib-Sequencer. 851 852 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_por_comp_ref_override_ctrl \ 853 0x00000010 // 1 - EN_POR_COMP_REF comes from 854 // bit[9] of the register 855 // MEM_HIB_MISC_CONTROLS [0x0044]. 0 856 // - EN_POR_COMP_REF comes directly 857 // from the Hib-Sequencer. 858 859 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_por_comp_override_ctrl \ 860 0x00000008 // 1 - EN_POR_COMP comes from 861 // bit[10] of the register 862 // MEM_HIB_MISC_CONTROLS [0x044]. 0 863 // - EN_POR_COMP comes directly from 864 // the Hib-Sequencer. 865 866 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_cap_sw_override_ctrl \ 867 0x00000004 // 1 - EN_CAP_SW comes from bit[1] 868 // of the register 869 // MEM_BGAP_PARAMETERS1 [0x003C]. 0 870 // - EN_CAP_SW comes directly from 871 // Hib-Sequencer. 872 873 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bg_override_ctrl \ 874 0x00000002 // 1 - EN_BGAP comes from bit[0] of 875 // the register MEM_BGAP_PARAMETERS1 876 // [0x003C]. 0 - EN_BGAP comes 877 // directly from Hib-Sequencer. 878 879 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_act_iref_override_ctrl \ 880 0x00000001 881 882 //****************************************************************************** 883 // 884 // The following are defines for the bit fields in the 885 // HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 register. 886 // 887 //****************************************************************************** 888 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_M \ 889 0xFFFF0000 890 891 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_S 16 892 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_M \ 893 0x0000C000 // Configuration for number of 894 // slow-clks between de-assertion of 895 // EN_COMP_LATCH and assertion of 896 897 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_S 14 898 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_M \ 899 0x00003000 // Configuration for number of 900 // slow-clks between assertion of 901 // EN_COMP_REF to assertion of 902 // EN_COMP during HIB-Exit 903 904 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_S 12 905 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_M \ 906 0x00000C00 // TBD 907 908 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_S 10 909 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_M \ 910 0x00000300 // Configuration in number of 911 // slow-clks between assertion of 912 // (EN_BGAP_3P3V, EN_CAP_SW_3P3V, 913 // EN_ACT_IREF_3P3V, EN_COMP_REF) to 914 // assertion of EN_COMP_3P3V 915 916 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_S 8 917 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_M \ 918 0x000000C0 // Configuration in number of 919 // slow-clks between de-assertion of 920 // (EN_COMP_3P3V, EN_COMP_REF_3P3V, 921 // EN_ACT_IREF_3P3V, EN_CAP_SW_3P3V) 922 // to deassertion of EN_BGAP_3P3V. 923 924 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_S 6 925 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_M \ 926 0x0000003F 927 928 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_S 0 929 //****************************************************************************** 930 // 931 // The following are defines for the bit fields in the 932 // HIB3P3_O_MEM_HIB_MISC_CONFIG register. 933 // 934 //****************************************************************************** 935 #define HIB3P3_MEM_HIB_MISC_CONFIG_mem_en_pll_untrim_current \ 936 0x00000001 937 938 //****************************************************************************** 939 // 940 // The following are defines for the bit fields in the 941 // HIB3P3_O_MEM_HIB_WAKE_STATUS register. 942 // 943 //****************************************************************************** 944 #define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_M \ 945 0x0000001E // "0100" - GPIO ; "0010" - RTC ; 946 // "0001" - UART Others - Reserved 947 948 #define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_S 1 949 #define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_status \ 950 0x00000001 // 1 - Wake from Hibernate ; 0 - 951 // Wake from OFF 952 953 //****************************************************************************** 954 // 955 // The following are defines for the bit fields in the 956 // HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL register. 957 // 958 //****************************************************************************** 959 #define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_M \ 960 0x00000007 961 962 #define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_S 0 963 //****************************************************************************** 964 // 965 // The following are defines for the bit fields in the 966 // HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 register. 967 // 968 //****************************************************************************** 969 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_M \ 970 0xFFFFF800 971 972 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_S 11 973 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_M \ 974 0x00000600 // Deassertion of EN_COMP_LATCH_3P3 975 // to deassertion of (EN_COMP_3P3, 976 // EN_COMP_REF_3P3, EN_ACT_IREF_3P3, 977 // EN_CAP_SW_3P3) 978 979 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_S 9 980 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_M \ 981 0x000001C0 // Assertion of EN_COMP_LATCH_3P3 982 // to deassertion of 983 // EN_COMP_LATCH_3P3 984 985 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_S 6 986 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_M \ 987 0x00000030 // Deassertion of (EN_CAP_SW_3P3, 988 // EN_COMP_REF_3P3, EN_COMP_3P3, 989 // EN_COMP_OUT_LATCH_3P3) to 990 // deassertion of EN_BGAP_3P3 991 992 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_S 4 993 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_M \ 994 0x0000000C // Assertion of EN_COMP_3P3 to 995 // assertion of EN_COMPOUT_LATCH_3P3 996 997 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_S 2 998 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_M \ 999 0x00000003 // Assertion of EN_COMP_3P3 to 1000 // assertion of EN_COMPOUT_LATCH_3P3 1001 1002 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_S 0 1003 //****************************************************************************** 1004 // 1005 // The following are defines for the bit fields in the 1006 // HIB3P3_O_HIBANA_SPARE_LOWV register. 1007 // 1008 //****************************************************************************** 1009 #define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_M \ 1010 0xFFC00000 1011 1012 #define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_S 22 1013 #define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_M \ 1014 0x0001FFFF 1015 1016 #define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_S 0 1017 //****************************************************************************** 1018 // 1019 // The following are defines for the bit fields in the 1020 // HIB3P3_O_HIB_TMUX_CTRL register. 1021 // 1022 //****************************************************************************** 1023 #define HIB3P3_HIB_TMUX_CTRL_reserved_M \ 1024 0xFFFFFC00 1025 1026 #define HIB3P3_HIB_TMUX_CTRL_reserved_S 10 1027 #define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_M \ 1028 0x000003FF 1029 1030 #define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_S 0 1031 //****************************************************************************** 1032 // 1033 // The following are defines for the bit fields in the 1034 // HIB3P3_O_HIB_1P2_1P8_LDO_TRIM register. 1035 // 1036 //****************************************************************************** 1037 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_M \ 1038 0xFFFFF000 1039 1040 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_S 12 1041 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override_ctrl \ 1042 0x00000800 1043 1044 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override_ctrl \ 1045 0x00000400 1046 1047 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override \ 1048 0x00000200 1049 1050 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override \ 1051 0x00000100 1052 1053 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_M \ 1054 0x000000F0 1055 1056 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_S 4 1057 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_M \ 1058 0x0000000F 1059 1060 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_S 0 1061 //****************************************************************************** 1062 // 1063 // The following are defines for the bit fields in the 1064 // HIB3P3_O_HIB_COMP_TRIM register. 1065 // 1066 //****************************************************************************** 1067 #define HIB3P3_HIB_COMP_TRIM_reserved_M \ 1068 0xFFFFFFF8 1069 1070 #define HIB3P3_HIB_COMP_TRIM_reserved_S 3 1071 #define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_M \ 1072 0x00000007 1073 1074 #define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_S 0 1075 //****************************************************************************** 1076 // 1077 // The following are defines for the bit fields in the 1078 // HIB3P3_O_HIB_EN_TS register. 1079 // 1080 //****************************************************************************** 1081 #define HIB3P3_HIB_EN_TS_reserved_M \ 1082 0xFFFFFFFE 1083 1084 #define HIB3P3_HIB_EN_TS_reserved_S 1 1085 #define HIB3P3_HIB_EN_TS_mem_hd_en_ts \ 1086 0x00000001 1087 1088 //****************************************************************************** 1089 // 1090 // The following are defines for the bit fields in the 1091 // HIB3P3_O_HIB_1P8V_DET_EN register. 1092 // 1093 //****************************************************************************** 1094 #define HIB3P3_HIB_1P8V_DET_EN_reserved_M \ 1095 0xFFFFFFFE 1096 1097 #define HIB3P3_HIB_1P8V_DET_EN_reserved_S 1 1098 #define HIB3P3_HIB_1P8V_DET_EN_mem_hib_1p8v_det_en \ 1099 0x00000001 1100 1101 //****************************************************************************** 1102 // 1103 // The following are defines for the bit fields in the 1104 // HIB3P3_O_HIB_VBAT_MON_EN register. 1105 // 1106 //****************************************************************************** 1107 #define HIB3P3_HIB_VBAT_MON_EN_reserved_M \ 1108 0xFFFFFFFC 1109 1110 #define HIB3P3_HIB_VBAT_MON_EN_reserved_S 2 1111 #define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_del_en \ 1112 0x00000002 1113 1114 #define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_en \ 1115 0x00000001 1116 1117 //****************************************************************************** 1118 // 1119 // The following are defines for the bit fields in the 1120 // HIB3P3_O_HIB_NHIB_ENABLE register. 1121 // 1122 //****************************************************************************** 1123 #define HIB3P3_HIB_NHIB_ENABLE_mem_hib_nhib_enable \ 1124 0x00000001 1125 1126 //****************************************************************************** 1127 // 1128 // The following are defines for the bit fields in the 1129 // HIB3P3_O_HIB_UART_RTS_SW_ENABLE register. 1130 // 1131 //****************************************************************************** 1132 #define HIB3P3_HIB_UART_RTS_SW_ENABLE_mem_hib_uart_rts_sw_enable \ 1133 0x00000001 1134 1135 1136 1137 1138 #endif // __HW_HIB3P3_H__ 1139