/dports/devel/avr-gdb/gdb-7.3.1/sim/m32r/ |
H A D | m32r2.c | 65 case H_CR_SPU : /* User stack pointer. */ in m32r2f_h_cr_get_handler() 69 return CPU (h_cr[H_CR_SPU]); in m32r2f_h_cr_get_handler() 100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler() 107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32r2f_h_cr_set_handler() 124 case H_CR_SPU : /* user stack pointer */ in m32r2f_h_cr_set_handler() 128 CPU (h_cr[H_CR_SPU]) = newval; in m32r2f_h_cr_set_handler()
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H A D | m32rx.c | 65 case H_CR_SPU : /* user stack pointer */ in m32rxf_h_cr_get_handler() 69 return CPU (h_cr[H_CR_SPU]); in m32rxf_h_cr_get_handler() 100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler() 107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rxf_h_cr_set_handler() 124 case H_CR_SPU : /* user stack pointer */ in m32rxf_h_cr_set_handler() 128 CPU (h_cr[H_CR_SPU]) = newval; in m32rxf_h_cr_set_handler()
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H A D | m32r.c | 38 case SPU_REGNUM : return H_CR_SPU; in m32r_decode_gdb_ctrl_regnum() 146 case H_CR_SPU : /* user stack pointer */ in m32rbf_h_cr_get_handler() 150 return CPU (h_cr[H_CR_SPU]); in m32rbf_h_cr_get_handler() 181 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler() 188 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rbf_h_cr_set_handler() 205 case H_CR_SPU : /* user stack pointer */ in m32rbf_h_cr_set_handler() 209 CPU (h_cr[H_CR_SPU]) = newval; in m32rbf_h_cr_set_handler()
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/dports/devel/gdb761/gdb-7.6.1/sim/m32r/ |
H A D | m32r2.c | 64 case H_CR_SPU : /* User stack pointer. */ in m32r2f_h_cr_get_handler() 68 return CPU (h_cr[H_CR_SPU]); in m32r2f_h_cr_get_handler() 99 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler() 106 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32r2f_h_cr_set_handler() 123 case H_CR_SPU : /* user stack pointer */ in m32r2f_h_cr_set_handler() 127 CPU (h_cr[H_CR_SPU]) = newval; in m32r2f_h_cr_set_handler()
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H A D | m32rx.c | 64 case H_CR_SPU : /* user stack pointer */ in m32rxf_h_cr_get_handler() 68 return CPU (h_cr[H_CR_SPU]); in m32rxf_h_cr_get_handler() 99 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler() 106 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rxf_h_cr_set_handler() 123 case H_CR_SPU : /* user stack pointer */ in m32rxf_h_cr_set_handler() 127 CPU (h_cr[H_CR_SPU]) = newval; in m32rxf_h_cr_set_handler()
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H A D | m32r.c | 37 case SPU_REGNUM : return H_CR_SPU; in m32r_decode_gdb_ctrl_regnum() 145 case H_CR_SPU : /* user stack pointer */ in m32rbf_h_cr_get_handler() 149 return CPU (h_cr[H_CR_SPU]); in m32rbf_h_cr_get_handler() 180 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler() 187 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rbf_h_cr_set_handler() 204 case H_CR_SPU : /* user stack pointer */ in m32rbf_h_cr_set_handler() 208 CPU (h_cr[H_CR_SPU]) = newval; in m32rbf_h_cr_set_handler()
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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/m32r/ |
H A D | m32r2.c | 65 case H_CR_SPU : /* User stack pointer. */ in m32r2f_h_cr_get_handler() 69 return CPU (h_cr[H_CR_SPU]); in m32r2f_h_cr_get_handler() 100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler() 107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32r2f_h_cr_set_handler() 124 case H_CR_SPU : /* user stack pointer */ in m32r2f_h_cr_set_handler() 128 CPU (h_cr[H_CR_SPU]) = newval; in m32r2f_h_cr_set_handler()
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H A D | m32rx.c | 65 case H_CR_SPU : /* user stack pointer */ in m32rxf_h_cr_get_handler() 69 return CPU (h_cr[H_CR_SPU]); in m32rxf_h_cr_get_handler() 100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler() 107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rxf_h_cr_set_handler() 124 case H_CR_SPU : /* user stack pointer */ in m32rxf_h_cr_set_handler() 128 CPU (h_cr[H_CR_SPU]) = newval; in m32rxf_h_cr_set_handler()
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H A D | m32r.c | 38 case SPU_REGNUM : return H_CR_SPU; in m32r_decode_gdb_ctrl_regnum() 146 case H_CR_SPU : /* user stack pointer */ in m32rbf_h_cr_get_handler() 150 return CPU (h_cr[H_CR_SPU]); in m32rbf_h_cr_get_handler() 181 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler() 188 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rbf_h_cr_set_handler() 205 case H_CR_SPU : /* user stack pointer */ in m32rbf_h_cr_set_handler() 209 CPU (h_cr[H_CR_SPU]) = newval; in m32rbf_h_cr_set_handler()
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/m32r/ |
H A D | m32rx.c | 65 case H_CR_SPU : /* user stack pointer */ in m32rxf_h_cr_get_handler() 69 return CPU (h_cr[H_CR_SPU]); in m32rxf_h_cr_get_handler() 100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler() 107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rxf_h_cr_set_handler() 124 case H_CR_SPU : /* user stack pointer */ in m32rxf_h_cr_set_handler() 128 CPU (h_cr[H_CR_SPU]) = newval; in m32rxf_h_cr_set_handler()
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H A D | m32r2.c | 65 case H_CR_SPU : /* User stack pointer. */ in m32r2f_h_cr_get_handler() 69 return CPU (h_cr[H_CR_SPU]); in m32r2f_h_cr_get_handler() 100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler() 107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32r2f_h_cr_set_handler() 124 case H_CR_SPU : /* user stack pointer */ in m32r2f_h_cr_set_handler() 128 CPU (h_cr[H_CR_SPU]) = newval; in m32r2f_h_cr_set_handler()
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H A D | m32r.c | 38 case SPU_REGNUM : return H_CR_SPU; in m32r_decode_gdb_ctrl_regnum() 146 case H_CR_SPU : /* user stack pointer */ in m32rbf_h_cr_get_handler() 150 return CPU (h_cr[H_CR_SPU]); in m32rbf_h_cr_get_handler() 181 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler() 188 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rbf_h_cr_set_handler() 205 case H_CR_SPU : /* user stack pointer */ in m32rbf_h_cr_set_handler() 209 CPU (h_cr[H_CR_SPU]) = newval; in m32rbf_h_cr_set_handler()
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/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/ |
H A D | m32r-desc.h | 93 H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 enumerator
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | m32r-desc.h | 93 H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 enumerator
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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | m32r-desc.h | 93 H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 enumerator
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/dports/devel/djgpp-binutils/binutils-2.17/opcodes/ |
H A D | m32r-desc.h | 95 H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 enumerator
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/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/ |
H A D | m32r-desc.h | 89 H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 enumerator
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/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/ |
H A D | m32r-desc.h | 94 H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 enumerator
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/dports/devel/avr-gdb/gdb-7.3.1/opcodes/ |
H A D | m32r-desc.h | 89 H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 enumerator
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/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/ |
H A D | m32r-desc.h | 89 H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 enumerator
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/dports/devel/gdb/gdb-11.1/opcodes/ |
H A D | m32r-desc.h | 94 H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 enumerator
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/dports/devel/gdb761/gdb-7.6.1/opcodes/ |
H A D | m32r-desc.h | 89 H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 enumerator
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/dports/devel/gnulibiberty/binutils-2.37/opcodes/ |
H A D | m32r-desc.h | 94 H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 enumerator
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/dports/devel/binutils/binutils-2.37/opcodes/ |
H A D | m32r-desc.h | 94 H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 enumerator
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