Home
last modified time | relevance | path

Searched refs:H_GR_SP (Results 1 – 25 of 72) sorted by relevance

123

/dports/devel/avr-gdb/gdb-7.3.1/sim/m32r/
H A Dm32r2.c62 return CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_get_handler()
67 return CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_get_handler()
100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler()
101 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32r2f_h_cr_set_handler()
106 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler()
107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32r2f_h_cr_set_handler()
120 CPU (h_gr[H_GR_SP]) = newval; in m32r2f_h_cr_set_handler()
126 CPU (h_gr[H_GR_SP]) = newval; in m32r2f_h_cr_set_handler()
H A Dm32rx.c62 return CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_get_handler()
67 return CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_get_handler()
100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler()
101 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32rxf_h_cr_set_handler()
106 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler()
107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rxf_h_cr_set_handler()
120 CPU (h_gr[H_GR_SP]) = newval; in m32rxf_h_cr_set_handler()
126 CPU (h_gr[H_GR_SP]) = newval; in m32rxf_h_cr_set_handler()
H A Dm32r.c143 return CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_get_handler()
148 return CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_get_handler()
181 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler()
182 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32rbf_h_cr_set_handler()
187 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler()
188 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rbf_h_cr_set_handler()
201 CPU (h_gr[H_GR_SP]) = newval; in m32rbf_h_cr_set_handler()
207 CPU (h_gr[H_GR_SP]) = newval; in m32rbf_h_cr_set_handler()
/dports/devel/gdb761/gdb-7.6.1/sim/m32r/
H A Dm32r2.c61 return CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_get_handler()
66 return CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_get_handler()
99 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler()
100 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32r2f_h_cr_set_handler()
105 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler()
106 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32r2f_h_cr_set_handler()
119 CPU (h_gr[H_GR_SP]) = newval; in m32r2f_h_cr_set_handler()
125 CPU (h_gr[H_GR_SP]) = newval; in m32r2f_h_cr_set_handler()
H A Dm32rx.c61 return CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_get_handler()
66 return CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_get_handler()
99 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler()
100 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32rxf_h_cr_set_handler()
105 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler()
106 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rxf_h_cr_set_handler()
119 CPU (h_gr[H_GR_SP]) = newval; in m32rxf_h_cr_set_handler()
125 CPU (h_gr[H_GR_SP]) = newval; in m32rxf_h_cr_set_handler()
H A Dm32r.c142 return CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_get_handler()
147 return CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_get_handler()
180 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler()
181 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32rbf_h_cr_set_handler()
186 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler()
187 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rbf_h_cr_set_handler()
200 CPU (h_gr[H_GR_SP]) = newval; in m32rbf_h_cr_set_handler()
206 CPU (h_gr[H_GR_SP]) = newval; in m32rbf_h_cr_set_handler()
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/m32r/
H A Dm32r2.c62 return CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_get_handler()
67 return CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_get_handler()
100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler()
101 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32r2f_h_cr_set_handler()
106 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler()
107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32r2f_h_cr_set_handler()
120 CPU (h_gr[H_GR_SP]) = newval; in m32r2f_h_cr_set_handler()
126 CPU (h_gr[H_GR_SP]) = newval; in m32r2f_h_cr_set_handler()
H A Dm32rx.c62 return CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_get_handler()
67 return CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_get_handler()
100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler()
101 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32rxf_h_cr_set_handler()
106 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler()
107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rxf_h_cr_set_handler()
120 CPU (h_gr[H_GR_SP]) = newval; in m32rxf_h_cr_set_handler()
126 CPU (h_gr[H_GR_SP]) = newval; in m32rxf_h_cr_set_handler()
H A Dm32r.c143 return CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_get_handler()
148 return CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_get_handler()
181 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler()
182 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32rbf_h_cr_set_handler()
187 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler()
188 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rbf_h_cr_set_handler()
201 CPU (h_gr[H_GR_SP]) = newval; in m32rbf_h_cr_set_handler()
207 CPU (h_gr[H_GR_SP]) = newval; in m32rbf_h_cr_set_handler()
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/m32r/
H A Dm32rx.c62 return CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_get_handler()
67 return CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_get_handler()
100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler()
101 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32rxf_h_cr_set_handler()
106 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler()
107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rxf_h_cr_set_handler()
120 CPU (h_gr[H_GR_SP]) = newval; in m32rxf_h_cr_set_handler()
126 CPU (h_gr[H_GR_SP]) = newval; in m32rxf_h_cr_set_handler()
H A Dm32r2.c62 return CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_get_handler()
67 return CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_get_handler()
100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler()
101 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32r2f_h_cr_set_handler()
106 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler()
107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32r2f_h_cr_set_handler()
120 CPU (h_gr[H_GR_SP]) = newval; in m32r2f_h_cr_set_handler()
126 CPU (h_gr[H_GR_SP]) = newval; in m32r2f_h_cr_set_handler()
H A Dm32r.c143 return CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_get_handler()
148 return CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_get_handler()
181 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler()
182 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32rbf_h_cr_set_handler()
187 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler()
188 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rbf_h_cr_set_handler()
201 CPU (h_gr[H_GR_SP]) = newval; in m32rbf_h_cr_set_handler()
207 CPU (h_gr[H_GR_SP]) = newval; in m32rbf_h_cr_set_handler()
/dports/devel/avr-gdb/gdb-7.3.1/sim/cris/
H A Dcrisv32f.c599 SET_H_SR (H_SR_USP, GET_H_GR (H_GR_SP)); in MY()
600 SET_H_GR (H_GR_SP, GET_H_KERNEL_SP ()); in MY()
H A Dtraps.c1183 (*CPU_REG_FETCH (current_cpu)) (current_cpu, H_GR_SP, regbuf, 4); in schedule()
1231 (*CPU_REG_STORE (current_cpu)) (current_cpu, H_GR_SP, regbuf, 4); in schedule()
2555 H_GR_SP, regbuf, 4); in cris_break_13_handler()
3145 H_GR_SP, old_sp_buf, 4); in cris_break_13_handler()
3148 H_GR_SP, sp_buf, 4); in cris_break_13_handler()
3156 H_GR_SP, old_sp_buf, 4); in cris_break_13_handler()
/dports/devel/gdb761/gdb-7.6.1/sim/cris/
H A Dcrisv32f.c598 SET_H_SR (H_SR_USP, GET_H_GR (H_GR_SP)); in MY()
599 SET_H_GR (H_GR_SP, GET_H_KERNEL_SP ()); in MY()
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/
H A Dm32r-desc.h84 H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0 enumerator
H A Dxstormy16-desc.h70 , H_GR_PSW = 14, H_GR_SP = 15 enumerator
H A Dfr30-desc.h112 , H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15 enumerator
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Dm32r-desc.h84 H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0 enumerator
H A Dfr30-desc.h112 , H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15 enumerator
H A Dxstormy16-desc.h70 , H_GR_PSW = 14, H_GR_SP = 15 enumerator
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Dm32r-desc.h84 H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0 enumerator
H A Dxstormy16-desc.h70 , H_GR_PSW = 14, H_GR_SP = 15
H A Dfr30-desc.h112 , H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15 enumerator
/dports/devel/djgpp-binutils/binutils-2.17/opcodes/
H A Dm32r-desc.h86 H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0 enumerator

123