/dports/devel/avr-gdb/gdb-7.3.1/sim/m32r/ |
H A D | m32r2.c | 62 return CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_get_handler() 67 return CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_get_handler() 100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler() 101 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32r2f_h_cr_set_handler() 106 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler() 107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32r2f_h_cr_set_handler() 120 CPU (h_gr[H_GR_SP]) = newval; in m32r2f_h_cr_set_handler() 126 CPU (h_gr[H_GR_SP]) = newval; in m32r2f_h_cr_set_handler()
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H A D | m32rx.c | 62 return CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_get_handler() 67 return CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_get_handler() 100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler() 101 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32rxf_h_cr_set_handler() 106 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler() 107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rxf_h_cr_set_handler() 120 CPU (h_gr[H_GR_SP]) = newval; in m32rxf_h_cr_set_handler() 126 CPU (h_gr[H_GR_SP]) = newval; in m32rxf_h_cr_set_handler()
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H A D | m32r.c | 143 return CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_get_handler() 148 return CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_get_handler() 181 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler() 182 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32rbf_h_cr_set_handler() 187 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler() 188 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rbf_h_cr_set_handler() 201 CPU (h_gr[H_GR_SP]) = newval; in m32rbf_h_cr_set_handler() 207 CPU (h_gr[H_GR_SP]) = newval; in m32rbf_h_cr_set_handler()
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/dports/devel/gdb761/gdb-7.6.1/sim/m32r/ |
H A D | m32r2.c | 61 return CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_get_handler() 66 return CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_get_handler() 99 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler() 100 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32r2f_h_cr_set_handler() 105 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler() 106 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32r2f_h_cr_set_handler() 119 CPU (h_gr[H_GR_SP]) = newval; in m32r2f_h_cr_set_handler() 125 CPU (h_gr[H_GR_SP]) = newval; in m32r2f_h_cr_set_handler()
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H A D | m32rx.c | 61 return CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_get_handler() 66 return CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_get_handler() 99 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler() 100 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32rxf_h_cr_set_handler() 105 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler() 106 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rxf_h_cr_set_handler() 119 CPU (h_gr[H_GR_SP]) = newval; in m32rxf_h_cr_set_handler() 125 CPU (h_gr[H_GR_SP]) = newval; in m32rxf_h_cr_set_handler()
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H A D | m32r.c | 142 return CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_get_handler() 147 return CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_get_handler() 180 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler() 181 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32rbf_h_cr_set_handler() 186 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler() 187 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rbf_h_cr_set_handler() 200 CPU (h_gr[H_GR_SP]) = newval; in m32rbf_h_cr_set_handler() 206 CPU (h_gr[H_GR_SP]) = newval; in m32rbf_h_cr_set_handler()
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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/m32r/ |
H A D | m32r2.c | 62 return CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_get_handler() 67 return CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_get_handler() 100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler() 101 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32r2f_h_cr_set_handler() 106 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler() 107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32r2f_h_cr_set_handler() 120 CPU (h_gr[H_GR_SP]) = newval; in m32r2f_h_cr_set_handler() 126 CPU (h_gr[H_GR_SP]) = newval; in m32r2f_h_cr_set_handler()
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H A D | m32rx.c | 62 return CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_get_handler() 67 return CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_get_handler() 100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler() 101 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32rxf_h_cr_set_handler() 106 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler() 107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rxf_h_cr_set_handler() 120 CPU (h_gr[H_GR_SP]) = newval; in m32rxf_h_cr_set_handler() 126 CPU (h_gr[H_GR_SP]) = newval; in m32rxf_h_cr_set_handler()
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H A D | m32r.c | 143 return CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_get_handler() 148 return CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_get_handler() 181 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler() 182 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32rbf_h_cr_set_handler() 187 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler() 188 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rbf_h_cr_set_handler() 201 CPU (h_gr[H_GR_SP]) = newval; in m32rbf_h_cr_set_handler() 207 CPU (h_gr[H_GR_SP]) = newval; in m32rbf_h_cr_set_handler()
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/m32r/ |
H A D | m32rx.c | 62 return CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_get_handler() 67 return CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_get_handler() 100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler() 101 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32rxf_h_cr_set_handler() 106 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler() 107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rxf_h_cr_set_handler() 120 CPU (h_gr[H_GR_SP]) = newval; in m32rxf_h_cr_set_handler() 126 CPU (h_gr[H_GR_SP]) = newval; in m32rxf_h_cr_set_handler()
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H A D | m32r2.c | 62 return CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_get_handler() 67 return CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_get_handler() 100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler() 101 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32r2f_h_cr_set_handler() 106 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler() 107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32r2f_h_cr_set_handler() 120 CPU (h_gr[H_GR_SP]) = newval; in m32r2f_h_cr_set_handler() 126 CPU (h_gr[H_GR_SP]) = newval; in m32r2f_h_cr_set_handler()
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H A D | m32r.c | 143 return CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_get_handler() 148 return CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_get_handler() 181 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler() 182 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32rbf_h_cr_set_handler() 187 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler() 188 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rbf_h_cr_set_handler() 201 CPU (h_gr[H_GR_SP]) = newval; in m32rbf_h_cr_set_handler() 207 CPU (h_gr[H_GR_SP]) = newval; in m32rbf_h_cr_set_handler()
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/dports/devel/avr-gdb/gdb-7.3.1/sim/cris/ |
H A D | crisv32f.c | 599 SET_H_SR (H_SR_USP, GET_H_GR (H_GR_SP)); in MY() 600 SET_H_GR (H_GR_SP, GET_H_KERNEL_SP ()); in MY()
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H A D | traps.c | 1183 (*CPU_REG_FETCH (current_cpu)) (current_cpu, H_GR_SP, regbuf, 4); in schedule() 1231 (*CPU_REG_STORE (current_cpu)) (current_cpu, H_GR_SP, regbuf, 4); in schedule() 2555 H_GR_SP, regbuf, 4); in cris_break_13_handler() 3145 H_GR_SP, old_sp_buf, 4); in cris_break_13_handler() 3148 H_GR_SP, sp_buf, 4); in cris_break_13_handler() 3156 H_GR_SP, old_sp_buf, 4); in cris_break_13_handler()
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/dports/devel/gdb761/gdb-7.6.1/sim/cris/ |
H A D | crisv32f.c | 598 SET_H_SR (H_SR_USP, GET_H_GR (H_GR_SP)); in MY() 599 SET_H_GR (H_GR_SP, GET_H_KERNEL_SP ()); in MY()
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/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/ |
H A D | m32r-desc.h | 84 H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0 enumerator
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H A D | xstormy16-desc.h | 70 , H_GR_PSW = 14, H_GR_SP = 15 enumerator
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H A D | fr30-desc.h | 112 , H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15 enumerator
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | m32r-desc.h | 84 H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0 enumerator
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H A D | fr30-desc.h | 112 , H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15 enumerator
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H A D | xstormy16-desc.h | 70 , H_GR_PSW = 14, H_GR_SP = 15 enumerator
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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | m32r-desc.h | 84 H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0 enumerator
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H A D | xstormy16-desc.h | 70 , H_GR_PSW = 14, H_GR_SP = 15
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H A D | fr30-desc.h | 112 , H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15 enumerator
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/dports/devel/djgpp-binutils/binutils-2.17/opcodes/ |
H A D | m32r-desc.h | 86 H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0 enumerator
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