Home
last modified time | relevance | path

Searched refs:HwConf (Results 1 – 12 of 12) sorted by relevance

/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
H A DLan9118DxeUtil.c465 UINT32 HwConf; in SoftReset() local
476 HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG); in SoftReset()
477 HwConf |= 1; in SoftReset()
480 if (((HwConf & HWCFG_MBO) >> 20) == 0) { in SoftReset()
481 HwConf |= HWCFG_MBO; in SoftReset()
488 Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf); in SoftReset()
926 UINT32 HwConf; in ChangeFifoAllocation() local
947 TxFifoOption = (HwConf >> 16) & 0xF; in ChangeFifoAllocation()
1018 HwConf = 0; in ChangeFifoAllocation()
1027 HwConf &= ~(0xF0000); in ChangeFifoAllocation()
[all …]
H A DLan9118Dxe.c374 UINT32 HwConf; in SnpReset() local
379 HwConf = 0; in SnpReset()
435 HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG); // Read the HW register in SnpReset()
436 HwConf &= ~HW_CFG_TX_FIFO_SIZE_MASK; // Clear buffer bits first in SnpReset()
437 HwConf |= HW_CFG_TX_FIFO_SIZE(gTxBuffer); // assign size chosen in SnpInitialize in SnpReset()
439 Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf); // Write the conf in SnpReset()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
H A DLan9118DxeUtil.c465 UINT32 HwConf; in SoftReset() local
476 HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG); in SoftReset()
477 HwConf |= 1; in SoftReset()
480 if (((HwConf & HWCFG_MBO) >> 20) == 0) { in SoftReset()
481 HwConf |= HWCFG_MBO; in SoftReset()
488 Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf); in SoftReset()
926 UINT32 HwConf; in ChangeFifoAllocation() local
947 TxFifoOption = (HwConf >> 16) & 0xF; in ChangeFifoAllocation()
1018 HwConf = 0; in ChangeFifoAllocation()
1027 HwConf &= ~(0xF0000); in ChangeFifoAllocation()
[all …]
H A DLan9118Dxe.c374 UINT32 HwConf; in SnpReset() local
379 HwConf = 0; in SnpReset()
435 HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG); // Read the HW register in SnpReset()
436 HwConf &= ~HW_CFG_TX_FIFO_SIZE_MASK; // Clear buffer bits first in SnpReset()
437 HwConf |= HW_CFG_TX_FIFO_SIZE(gTxBuffer); // assign size chosen in SnpInitialize in SnpReset()
439 Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf); // Write the conf in SnpReset()
/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/EmbeddedPkg/Drivers/Lan9118Dxe/
H A DLan9118DxeUtil.c465 UINT32 HwConf; in SoftReset() local
476 HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG); in SoftReset()
477 HwConf |= 1; in SoftReset()
480 if (((HwConf & HWCFG_MBO) >> 20) == 0) { in SoftReset()
481 HwConf |= HWCFG_MBO; in SoftReset()
488 Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf); in SoftReset()
926 UINT32 HwConf; in ChangeFifoAllocation() local
947 TxFifoOption = (HwConf >> 16) & 0xF; in ChangeFifoAllocation()
1018 HwConf = 0; in ChangeFifoAllocation()
1027 HwConf &= ~(0xF0000); in ChangeFifoAllocation()
[all …]
H A DLan9118Dxe.c375 UINT32 HwConf; in SnpReset() local
380 HwConf = 0; in SnpReset()
436 HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG); // Read the HW register in SnpReset()
437 HwConf &= ~HW_CFG_TX_FIFO_SIZE_MASK; // Clear buffer bits first in SnpReset()
438 HwConf |= HW_CFG_TX_FIFO_SIZE(gTxBuffer); // assign size chosen in SnpInitialize in SnpReset()
440 Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf); // Write the conf in SnpReset()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
H A DLan9118DxeUtil.c465 UINT32 HwConf; in SoftReset() local
476 HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG); in SoftReset()
477 HwConf |= 1; in SoftReset()
480 if (((HwConf & HWCFG_MBO) >> 20) == 0) { in SoftReset()
481 HwConf |= HWCFG_MBO; in SoftReset()
488 Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf); in SoftReset()
926 UINT32 HwConf; in ChangeFifoAllocation() local
947 TxFifoOption = (HwConf >> 16) & 0xF; in ChangeFifoAllocation()
1018 HwConf = 0; in ChangeFifoAllocation()
1027 HwConf &= ~(0xF0000); in ChangeFifoAllocation()
[all …]
H A DLan9118Dxe.c374 UINT32 HwConf; in SnpReset() local
379 HwConf = 0; in SnpReset()
435 HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG); // Read the HW register in SnpReset()
436 HwConf &= ~HW_CFG_TX_FIFO_SIZE_MASK; // Clear buffer bits first in SnpReset()
437 HwConf |= HW_CFG_TX_FIFO_SIZE(gTxBuffer); // assign size chosen in SnpInitialize in SnpReset()
439 Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf); // Write the conf in SnpReset()
/dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/ARM/VExpressPkg/Drivers/Lan9118Dxe/
H A DLan9118DxeUtil.c472 UINT32 HwConf; in SoftReset() local
483 HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG); in SoftReset()
484 HwConf |= 1; in SoftReset()
487 if (((HwConf & HWCFG_MBO) >> 20) == 0) { in SoftReset()
488 HwConf |= HWCFG_MBO; in SoftReset()
495 Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf); in SoftReset()
933 UINT32 HwConf; in ChangeFifoAllocation() local
954 TxFifoOption = (HwConf >> 16) & 0xF; in ChangeFifoAllocation()
1025 HwConf = 0; in ChangeFifoAllocation()
1034 HwConf &= ~(0xF0000); in ChangeFifoAllocation()
[all …]
H A DLan9118Dxe.c382 UINT32 HwConf; in SnpReset() local
387 HwConf = 0; in SnpReset()
443 HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG); // Read the HW register in SnpReset()
444 HwConf &= ~HW_CFG_TX_FIFO_SIZE_MASK; // Clear buffer bits first in SnpReset()
445 HwConf |= HW_CFG_TX_FIFO_SIZE(gTxBuffer); // assign size chosen in SnpInitialize in SnpReset()
447 Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf); // Write the conf in SnpReset()
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/EmbeddedPkg/Drivers/Lan9118Dxe/
H A DLan9118DxeUtil.c427 UINT32 HwConf; in SoftReset() local
438 HwConf = MmioRead32 (LAN9118_HW_CFG); in SoftReset()
439 HwConf |= 1; in SoftReset()
442 if (((HwConf & HWCFG_MBO) >> 20) == 0) { in SoftReset()
443 HwConf |= HWCFG_MBO; in SoftReset()
450 MmioWrite32 (LAN9118_HW_CFG, HwConf); in SoftReset()
914 UINT32 HwConf; in ChangeFifoAllocation() local
935 TxFifoOption = (HwConf >> 16) & 0xF; in ChangeFifoAllocation()
1006 HwConf = 0; in ChangeFifoAllocation()
1015 HwConf &= ~(0xF0000); in ChangeFifoAllocation()
[all …]
H A DLan9118Dxe.c380 UINT32 HwConf; in SnpReset() local
385 HwConf = 0; in SnpReset()
436 HwConf = MmioRead32 (LAN9118_HW_CFG); // Read the HW register in SnpReset()
437 HwConf &= ~HW_CFG_TX_FIFO_SIZE_MASK; // Clear buffer bits first in SnpReset()
438 HwConf |= HW_CFG_TX_FIFO_SIZE(gTxBuffer); // assign size chosen in SnpInitialize in SnpReset()
440 MmioWrite32 (LAN9118_HW_CFG, HwConf); // Write the conf in SnpReset()