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/dports/cad/yosys/yosys-yosys-0.12/techlibs/xilinx/
H A Dcells_sim.v142 wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT); net
146 assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);