1 //***************************************************************************** 2 // 3 // Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 4 // 5 // 6 // Redistribution and use in source and binary forms, with or without 7 // modification, are permitted provided that the following conditions 8 // are met: 9 // 10 // Redistributions of source code must retain the above copyright 11 // notice, this list of conditions and the following disclaimer. 12 // 13 // Redistributions in binary form must reproduce the above copyright 14 // notice, this list of conditions and the following disclaimer in the 15 // documentation and/or other materials provided with the 16 // distribution. 17 // 18 // Neither the name of Texas Instruments Incorporated nor the names of 19 // its contributors may be used to endorse or promote products derived 20 // from this software without specific prior written permission. 21 // 22 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 26 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 28 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 // 34 //***************************************************************************** 35 36 #ifndef __HW_I2C_H__ 37 #define __HW_I2C_H__ 38 39 //***************************************************************************** 40 // 41 // The following are defines for the I2C register offsets. 42 // 43 //***************************************************************************** 44 #define I2C_O_MSA 0x00000000 45 #define I2C_O_MCS 0x00000004 46 #define I2C_O_MDR 0x00000008 47 #define I2C_O_MTPR 0x0000000C 48 #define I2C_O_MIMR 0x00000010 49 #define I2C_O_MRIS 0x00000014 50 #define I2C_O_MMIS 0x00000018 51 #define I2C_O_MICR 0x0000001C 52 #define I2C_O_MCR 0x00000020 53 #define I2C_O_MCLKOCNT 0x00000024 54 #define I2C_O_MBMON 0x0000002C 55 #define I2C_O_MBLEN 0x00000030 56 #define I2C_O_MBCNT 0x00000034 57 #define I2C_O_SOAR 0x00000800 58 #define I2C_O_SCSR 0x00000804 59 #define I2C_O_SDR 0x00000808 60 #define I2C_O_SIMR 0x0000080C 61 #define I2C_O_SRIS 0x00000810 62 #define I2C_O_SMIS 0x00000814 63 #define I2C_O_SICR 0x00000818 64 #define I2C_O_SOAR2 0x0000081C 65 #define I2C_O_SACKCTL 0x00000820 66 #define I2C_O_FIFODATA 0x00000F00 67 #define I2C_O_FIFOCTL 0x00000F04 68 #define I2C_O_FIFOSTATUS 0x00000F08 69 #define I2C_O_OBSMUXSEL0 0x00000F80 70 #define I2C_O_OBSMUXSEL1 0x00000F84 71 #define I2C_O_MUXROUTE 0x00000F88 72 #define I2C_O_PV 0x00000FB0 73 #define I2C_O_PP 0x00000FC0 74 #define I2C_O_PC 0x00000FC4 75 #define I2C_O_CC 0x00000FC8 76 77 78 79 //****************************************************************************** 80 // 81 // The following are defines for the bit fields in the I2C_O_MSA register. 82 // 83 //****************************************************************************** 84 #define I2C_MSA_SA_M 0x000000FE // I2C Slave Address 85 #define I2C_MSA_SA_S 1 86 #define I2C_MSA_RS 0x00000001 // Receive not send 87 //****************************************************************************** 88 // 89 // The following are defines for the bit fields in the I2C_O_MCS register. 90 // 91 //****************************************************************************** 92 #define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status 93 #define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status 94 #define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error 95 #define I2C_MCS_BUSBSY 0x00000040 // Bus Busy 96 #define I2C_MCS_IDLE 0x00000020 // I2C Idle 97 #define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost 98 #define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable 99 #define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address 100 #define I2C_MCS_ERROR 0x00000002 // Error 101 #define I2C_MCS_BUSY 0x00000001 // I2C Busy 102 //****************************************************************************** 103 // 104 // The following are defines for the bit fields in the I2C_O_MDR register. 105 // 106 //****************************************************************************** 107 #define I2C_MDR_DATA_M 0x000000FF // Data Transferred 108 #define I2C_MDR_DATA_S 0 109 //****************************************************************************** 110 // 111 // The following are defines for the bit fields in the I2C_O_MTPR register. 112 // 113 //****************************************************************************** 114 #define I2C_MTPR_HS 0x00000080 // High-Speed Enable 115 #define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period 116 #define I2C_MTPR_TPR_S 0 117 //****************************************************************************** 118 // 119 // The following are defines for the bit fields in the I2C_O_MIMR register. 120 // 121 //****************************************************************************** 122 #define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask 123 #define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt 124 // Mask 125 #define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt 126 // Mask 127 #define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt 128 // Mask 129 #define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask 130 #define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask 131 #define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask 132 #define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask 133 #define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask 134 #define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask 135 #define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask 136 #define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask 137 //****************************************************************************** 138 // 139 // The following are defines for the bit fields in the I2C_O_MRIS register. 140 // 141 //****************************************************************************** 142 #define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt 143 // Status 144 #define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw 145 // Interrupt Status 146 #define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw 147 // Interrupt Status 148 #define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt 149 // Status 150 #define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt 151 // Status 152 #define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt 153 // Status 154 #define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt 155 // Status 156 #define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt 157 // Status 158 #define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt 159 // Status 160 #define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status 161 #define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt 162 // Status 163 #define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status 164 //****************************************************************************** 165 // 166 // The following are defines for the bit fields in the I2C_O_MMIS register. 167 // 168 //****************************************************************************** 169 #define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask 170 #define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt 171 // Mask 172 #define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt 173 // Mask 174 #define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask 175 #define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask 176 #define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask 177 #define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask 178 #define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask 179 #define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status 180 #define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status 181 #define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt 182 // Status 183 #define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status 184 //****************************************************************************** 185 // 186 // The following are defines for the bit fields in the I2C_O_MICR register. 187 // 188 //****************************************************************************** 189 #define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt 190 // Clear 191 #define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt 192 // Clear 193 #define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt 194 // Clear 195 #define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt 196 // Clear 197 #define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear 198 #define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear 199 #define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear 200 #define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt 201 // Clear 202 #define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear 203 #define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear 204 #define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear 205 #define I2C_MICR_IC 0x00000001 // Master Interrupt Clear 206 //****************************************************************************** 207 // 208 // The following are defines for the bit fields in the I2C_O_MCR register. 209 // 210 //****************************************************************************** 211 #define I2C_MCR_MMD 0x00000040 // Multi-master Disable 212 #define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable 213 #define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable 214 #define I2C_MCR_LPBK 0x00000001 // I2C Loopback 215 //****************************************************************************** 216 // 217 // The following are defines for the bit fields in the I2C_O_MCLKOCNT register. 218 // 219 //****************************************************************************** 220 #define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count 221 #define I2C_MCLKOCNT_CNTL_S 0 222 //****************************************************************************** 223 // 224 // The following are defines for the bit fields in the I2C_O_MBMON register. 225 // 226 //****************************************************************************** 227 #define I2C_MBMON_SDA 0x00000002 // I2C SDA Status 228 #define I2C_MBMON_SCL 0x00000001 // I2C SCL Status 229 //****************************************************************************** 230 // 231 // The following are defines for the bit fields in the I2C_O_MBLEN register. 232 // 233 //****************************************************************************** 234 #define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length 235 #define I2C_MBLEN_CNTL_S 0 236 //****************************************************************************** 237 // 238 // The following are defines for the bit fields in the I2C_O_MBCNT register. 239 // 240 //****************************************************************************** 241 #define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count 242 #define I2C_MBCNT_CNTL_S 0 243 //****************************************************************************** 244 // 245 // The following are defines for the bit fields in the I2C_O_SOAR register. 246 // 247 //****************************************************************************** 248 #define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address 249 #define I2C_SOAR_OAR_S 0 250 //****************************************************************************** 251 // 252 // The following are defines for the bit fields in the I2C_O_SCSR register. 253 // 254 //****************************************************************************** 255 #define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status 256 #define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status 257 #define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write 258 #define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status 259 #define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched 260 #define I2C_SCSR_FBR 0x00000004 // First Byte Received 261 #define I2C_SCSR_TREQ 0x00000002 // Transmit Request 262 #define I2C_SCSR_DA 0x00000001 // Device Active 263 //****************************************************************************** 264 // 265 // The following are defines for the bit fields in the I2C_O_SDR register. 266 // 267 //****************************************************************************** 268 #define I2C_SDR_DATA_M 0x000000FF // Data for Transfer 269 #define I2C_SDR_DATA_S 0 270 //****************************************************************************** 271 // 272 // The following are defines for the bit fields in the I2C_O_SIMR register. 273 // 274 //****************************************************************************** 275 #define I2C_SIMR_IM 0x00000100 // Interrupt Mask 276 #define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt 277 // Mask 278 #define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt 279 // Mask 280 #define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt 281 // Mask 282 #define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask 283 #define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask 284 #define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask 285 #define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask 286 #define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask 287 //****************************************************************************** 288 // 289 // The following are defines for the bit fields in the I2C_O_SRIS register. 290 // 291 //****************************************************************************** 292 #define I2C_SRIS_RIS 0x00000100 // Raw Interrupt Status 293 #define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw 294 // Interrupt Status 295 #define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw 296 // Interrupt Status 297 #define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt 298 // Status 299 #define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt 300 // Status 301 #define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status 302 #define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt 303 // Status 304 #define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt 305 // Status 306 #define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status 307 //****************************************************************************** 308 // 309 // The following are defines for the bit fields in the I2C_O_SMIS register. 310 // 311 //****************************************************************************** 312 #define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask 313 #define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt 314 // Mask 315 #define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt 316 // Mask 317 #define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt 318 // Mask 319 #define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt 320 // Status 321 #define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt 322 // Status 323 #define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt 324 // Status 325 #define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt 326 // Status 327 #define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status 328 //****************************************************************************** 329 // 330 // The following are defines for the bit fields in the I2C_O_SICR register. 331 // 332 //****************************************************************************** 333 #define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask 334 #define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt 335 // Mask 336 #define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask 337 #define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask 338 #define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear 339 #define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear 340 #define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear 341 #define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear 342 #define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear 343 //****************************************************************************** 344 // 345 // The following are defines for the bit fields in the I2C_O_SOAR2 register. 346 // 347 //****************************************************************************** 348 #define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable 349 #define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 350 #define I2C_SOAR2_OAR2_S 0 351 //****************************************************************************** 352 // 353 // The following are defines for the bit fields in the I2C_O_SACKCTL register. 354 // 355 //****************************************************************************** 356 #define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value 357 #define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable 358 //****************************************************************************** 359 // 360 // The following are defines for the bit fields in the I2C_O_FIFODATA register. 361 // 362 //****************************************************************************** 363 #define I2C_FIFODATA_DATA_M 0x000000FF // I2C FIFO Data Byte 364 #define I2C_FIFODATA_DATA_S 0 365 //****************************************************************************** 366 // 367 // The following are defines for the bit fields in the I2C_O_FIFOCTL register. 368 // 369 //****************************************************************************** 370 #define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment 371 #define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush 372 #define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable 373 #define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger 374 #define I2C_FIFOCTL_RXTRIG_S 16 375 #define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment 376 #define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush 377 #define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable 378 #define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger 379 #define I2C_FIFOCTL_TXTRIG_S 0 380 //****************************************************************************** 381 // 382 // The following are defines for the bit fields in the I2C_O_FIFOSTATUS register. 383 // 384 //****************************************************************************** 385 #define I2C_FIFOSTATUS_RXABVTRIG \ 386 0x00040000 // RX FIFO Above Trigger Level 387 388 #define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full 389 #define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty 390 #define I2C_FIFOSTATUS_TXBLWTRIG \ 391 0x00000004 // TX FIFO Below Trigger Level 392 393 #define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full 394 #define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty 395 //****************************************************************************** 396 // 397 // The following are defines for the bit fields in the I2C_O_OBSMUXSEL0 register. 398 // 399 //****************************************************************************** 400 #define I2C_OBSMUXSEL0_LN3_M 0x07000000 // Observation Mux Lane 3 401 #define I2C_OBSMUXSEL0_LN3_S 24 402 #define I2C_OBSMUXSEL0_LN2_M 0x00070000 // Observation Mux Lane 2 403 #define I2C_OBSMUXSEL0_LN2_S 16 404 #define I2C_OBSMUXSEL0_LN1_M 0x00000700 // Observation Mux Lane 1 405 #define I2C_OBSMUXSEL0_LN1_S 8 406 #define I2C_OBSMUXSEL0_LN0_M 0x00000007 // Observation Mux Lane 0 407 #define I2C_OBSMUXSEL0_LN0_S 0 408 //****************************************************************************** 409 // 410 // The following are defines for the bit fields in the I2C_O_OBSMUXSEL1 register. 411 // 412 //****************************************************************************** 413 #define I2C_OBSMUXSEL1_LN7_M 0x07000000 // Observation Mux Lane 7 414 #define I2C_OBSMUXSEL1_LN7_S 24 415 #define I2C_OBSMUXSEL1_LN6_M 0x00070000 // Observation Mux Lane 6 416 #define I2C_OBSMUXSEL1_LN6_S 16 417 #define I2C_OBSMUXSEL1_LN5_M 0x00000700 // Observation Mux Lane 5 418 #define I2C_OBSMUXSEL1_LN5_S 8 419 #define I2C_OBSMUXSEL1_LN4_M 0x00000007 // Observation Mux Lane 4 420 #define I2C_OBSMUXSEL1_LN4_S 0 421 //****************************************************************************** 422 // 423 // The following are defines for the bit fields in the I2C_O_MUXROUTE register. 424 // 425 //****************************************************************************** 426 #define I2C_MUXROUTE_LN7ROUTE_M \ 427 0x70000000 // Lane 7 output is routed to the 428 // lane pointed to by the offset in 429 // this bit field 430 431 #define I2C_MUXROUTE_LN7ROUTE_S 28 432 #define I2C_MUXROUTE_LN6ROUTE_M \ 433 0x07000000 // Lane 6 output is routed to the 434 // lane pointed to by the offset in 435 // this bit field 436 437 #define I2C_MUXROUTE_LN6ROUTE_S 24 438 #define I2C_MUXROUTE_LN5ROUTE_M \ 439 0x00700000 // Lane 5 output is routed to the 440 // lane pointed to by the offset in 441 // this bit field 442 443 #define I2C_MUXROUTE_LN5ROUTE_S 20 444 #define I2C_MUXROUTE_LN4ROUTE_M \ 445 0x00070000 // Lane 4 output is routed to the 446 // lane pointed to by the offset in 447 // this bit field 448 449 #define I2C_MUXROUTE_LN4ROUTE_S 16 450 #define I2C_MUXROUTE_LN3ROUTE_M \ 451 0x00007000 // Lane 3 output is routed to the 452 // lane pointed to by the offset in 453 // this bit field 454 455 #define I2C_MUXROUTE_LN3ROUTE_S 12 456 #define I2C_MUXROUTE_LN2ROUTE_M \ 457 0x00000700 // Lane 2 output is routed to the 458 // lane pointed to by the offset in 459 // this bit field 460 461 #define I2C_MUXROUTE_LN2ROUTE_S 8 462 #define I2C_MUXROUTE_LN1ROUTE_M \ 463 0x00000070 // Lane 1 output is routed to the 464 // lane pointed to by the offset in 465 // this bit field 466 467 #define I2C_MUXROUTE_LN1ROUTE_S 4 468 #define I2C_MUXROUTE_LN0ROUTE_M \ 469 0x00000007 // Lane 0 output is routed to the 470 // lane pointed to by the offset in 471 // this bit field 472 473 #define I2C_MUXROUTE_LN0ROUTE_S 0 474 //****************************************************************************** 475 // 476 // The following are defines for the bit fields in the I2C_O_PV register. 477 // 478 //****************************************************************************** 479 #define I2C_PV_MAJOR_M 0x0000FF00 // Major Revision 480 #define I2C_PV_MAJOR_S 8 481 #define I2C_PV_MINOR_M 0x000000FF // Minor Revision 482 #define I2C_PV_MINOR_S 0 483 //****************************************************************************** 484 // 485 // The following are defines for the bit fields in the I2C_O_PP register. 486 // 487 //****************************************************************************** 488 #define I2C_PP_HS 0x00000001 // High-Speed Capable 489 //****************************************************************************** 490 // 491 // The following are defines for the bit fields in the I2C_O_PC register. 492 // 493 //****************************************************************************** 494 #define I2C_PC_HS 0x00000001 // High-Speed Capable 495 //****************************************************************************** 496 // 497 // The following are defines for the bit fields in the I2C_O_CC register. 498 // 499 //****************************************************************************** 500 501 502 503 #endif // __HW_I2C_H__ 504