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Searched refs:I65 (Results 1 – 25 of 149) sorted by relevance

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/dports/cad/qelectrotech/qet-0.7.0/elements/10_electric/20_manufacturers_articles/siemens/01_PLC&controllers/6es5/carte_sortie/
H A D6es5_482-8ma13__p3.elmt31 <input x="155" y="-6" size="7" rotate="true" text="I65.1"/>
34 <input x="635" y="-6" size="7" rotate="true" text="I65.7"/>
35 <input x="555" y="-6" size="7" rotate="true" text="I65.6"/>
36 <input x="475" y="-6" size="7" rotate="true" text="I65.5"/>
37 <input x="395" y="-6" size="7" rotate="true" text="I65.4"/>
38 <input x="315" y="-6" size="7" rotate="true" text="I65.3"/>
39 <input x="235" y="-6" size="7" rotate="true" text="I65.2"/>
56 <input x="75" y="-6" size="7" rotate="true" text="I65.0"/>
/dports/cad/qelectrotech/qet-0.7.0/elements/10_electric/20_manufacturers_articles/siemens/01_PLC&controllers/6es5/
H A D6es5_482-8ma13__p3.elmt30 <input x="155" y="-6" size="7" rotate="true" text="I65.1"/>
33 <input x="635" y="-6" size="7" rotate="true" text="I65.7"/>
34 <input x="555" y="-6" size="7" rotate="true" text="I65.6"/>
35 <input x="475" y="-6" size="7" rotate="true" text="I65.5"/>
36 <input x="395" y="-6" size="7" rotate="true" text="I65.4"/>
37 <input x="315" y="-6" size="7" rotate="true" text="I65.3"/>
38 <input x="235" y="-6" size="7" rotate="true" text="I65.2"/>
55 <input x="75" y="-6" size="7" rotate="true" text="I65.0"/>
/dports/science/openbabel/openbabel-3.1.1/test/pdb_ligands_sdf/
H A D3i65_jz8.sdf3 Coordinates from PDB:3I65:A:1001 Model:1 without hydrogens
101 3I65
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Dmips-opc.c90 #define I65 INSN_ISA64R2 macro
485 {"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, I65 },
499 {"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, I65 },
572 {"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, N5|I65 },
575 {"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I65 },
576 {"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I65 },
577 {"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I65 },
578 {"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I65 },
580 {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, I65 },
581 {"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, I65 },
[all …]
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/
H A Dmips-opc.c90 #define I65 INSN_ISA64R2 macro
481 {"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 },
495 {"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 },
566 {"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 },
569 {"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 },
570 {"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 },
571 {"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 },
572 {"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 },
574 {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 },
575 {"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 },
[all …]
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Dmips-opc.c90 #define I65 INSN_ISA64R2 macro
485 {"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, I65 },
499 {"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, I65 },
572 {"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, N5|I65 },
575 {"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I65 },
576 {"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I65 },
577 {"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I65 },
578 {"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I65 },
580 {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, I65 },
581 {"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, I65 },
[all …]
/dports/devel/djgpp-binutils/binutils-2.17/opcodes/
H A Dmips-opc.c90 #define I65 INSN_ISA64R2 macro
514 {"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 },
528 {"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 },
601 {"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 },
604 {"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 },
605 {"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 },
606 {"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 },
607 {"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 },
609 {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 },
610 {"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 },
[all …]
/dports/devel/spirv-llvm-translator/SPIRV-LLVM-Translator-13.0.0/test/
H A Dcapability-arbitrary-precision-integers.ll18 ; CHECK-SPIRV-DAG: TypeInt [[#I65:]] 65 0
25 ; CHECK-SPIRV-DAG: Constant [[#I65]] [[#]] 1 0 1
/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/mips/gnu/
H A Dmips-opc.c91 #define I65 INSN_ISA64R2 macro
558 {"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 },
572 {"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 },
643 {"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 },
646 {"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 },
647 {"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 },
648 {"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 },
649 {"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 },
651 {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 },
652 {"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 },
[all …]
/dports/devel/avr-gdb/gdb-7.3.1/opcodes/
H A Dmips-opc.c92 #define I65 INSN_ISA64R2 macro
635 {"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 },
649 {"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 },
722 {"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 },
725 {"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 },
726 {"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 },
727 {"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 },
728 {"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 },
730 {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 },
731 {"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 },
[all …]
/dports/devel/gdb761/gdb-7.6.1/opcodes/
H A Dmips-opc.c94 #define I65 INSN_ISA64R2 macro
665 {"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 },
680 {"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 },
757 {"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 },
760 {"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 },
761 {"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 },
762 {"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 },
763 {"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 },
765 {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 },
766 {"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 },
[all …]
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/
H A Dmips-dis.c1118 #define I65 INSN_ISA64R2 macro
1550 {"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 },
1564 {"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 },
1635 {"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 },
1638 {"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 },
1639 {"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 },
1640 {"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 },
1641 {"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 },
1643 {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 },
1644 {"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 },
[all …]
/dports/lang/zig/zig-0.9.0/test/behavior/
H A Denum.zig102 I65,
360 I65,
/dports/lang/zig-devel/zig-0.9.0/test/behavior/
H A Denum.zig102 I65,
360 I65,
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Mips/msa/
H A Dllvm-stress-s1704963983.ll112 %I65 = insertelement <8 x i64> %B22, i64 %L47, i32 7
113 %B66 = add <8 x i64> %I50, %I65
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/Mips/msa/
H A Dllvm-stress-s1704963983.ll112 %I65 = insertelement <8 x i64> %B22, i64 %L47, i32 7
113 %B66 = add <8 x i64> %I50, %I65
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Mips/msa/
H A Dllvm-stress-s1704963983.ll112 %I65 = insertelement <8 x i64> %B22, i64 %L47, i32 7
113 %B66 = add <8 x i64> %I50, %I65
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/msa/
H A Dllvm-stress-s1704963983.ll112 %I65 = insertelement <8 x i64> %B22, i64 %L47, i32 7
113 %B66 = add <8 x i64> %I50, %I65
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Mips/msa/
H A Dllvm-stress-s1704963983.ll112 %I65 = insertelement <8 x i64> %B22, i64 %L47, i32 7
113 %B66 = add <8 x i64> %I50, %I65
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/Mips/msa/
H A Dllvm-stress-s1704963983.ll112 %I65 = insertelement <8 x i64> %B22, i64 %L47, i32 7
113 %B66 = add <8 x i64> %I50, %I65
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/Mips/msa/
H A Dllvm-stress-s1704963983.ll112 %I65 = insertelement <8 x i64> %B22, i64 %L47, i32 7
113 %B66 = add <8 x i64> %I50, %I65
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/msa/
H A Dllvm-stress-s1704963983.ll112 %I65 = insertelement <8 x i64> %B22, i64 %L47, i32 7
113 %B66 = add <8 x i64> %I50, %I65
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/Mips/msa/
H A Dllvm-stress-s1704963983.ll112 %I65 = insertelement <8 x i64> %B22, i64 %L47, i32 7
113 %B66 = add <8 x i64> %I50, %I65
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/Mips/msa/
H A Dllvm-stress-s1704963983.ll112 %I65 = insertelement <8 x i64> %B22, i64 %L47, i32 7
113 %B66 = add <8 x i64> %I50, %I65
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/Mips/msa/
H A Dllvm-stress-s1704963983.ll112 %I65 = insertelement <8 x i64> %B22, i64 %L47, i32 7
113 %B66 = add <8 x i64> %I50, %I65

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