| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/irqchip/ |
| H A D | irq-renesas-rza1.c | 29 #define ICR1 2 /* Interrupt Control Register 1 */ macro
95 tmp = readw_relaxed(priv->base + ICR1); in rza1_irqc_set_type()
98 writew_relaxed(tmp, priv->base + ICR1); in rza1_irqc_set_type()
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/irqchip/ |
| H A D | irq-renesas-rza1.c | 29 #define ICR1 2 /* Interrupt Control Register 1 */ macro
95 tmp = readw_relaxed(priv->base + ICR1); in rza1_irqc_set_type()
98 writew_relaxed(tmp, priv->base + ICR1); in rza1_irqc_set_type()
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/irqchip/ |
| H A D | irq-renesas-rza1.c | 29 #define ICR1 2 /* Interrupt Control Register 1 */ macro
95 tmp = readw_relaxed(priv->base + ICR1); in rza1_irqc_set_type()
98 writew_relaxed(tmp, priv->base + ICR1); in rza1_irqc_set_type()
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| /dports/devel/asl/asl-current/include/coldfire/ |
| H A D | 52xxintc.inc | 72 ICR1{"\{__NS}"} equ MBAR_INTC1+$040+__N; Interrupt Control Register N (8b)
73 LEVEL cffield ICR1{"\{__NS}"},0,3 ; Interrupt level.
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| /dports/emulators/mess/mame-mame0226/src/devices/cpu/f2mc16/ |
| H A D | mb9061x.h | 31 …ICR0 = 0, ICR1, ICR2, ICR3, ICR4, ICR5, ICR6, ICR7, ICR8, ICR9, ICR10, ICR11, ICR12, ICR13, ICR14,… enumerator
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| /dports/emulators/mame/mame-mame0226/src/devices/cpu/f2mc16/ |
| H A D | mb9061x.h | 31 …ICR0 = 0, ICR1, ICR2, ICR3, ICR4, ICR5, ICR6, ICR7, ICR8, ICR9, ICR10, ICR11, ICR12, ICR13, ICR14,… enumerator
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| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/sh/include/asm/ |
| H A D | cpu_sh7720.h | 48 #define ICR1 0xA4140010 macro
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/sh/include/asm/ |
| H A D | cpu_sh7720.h | 48 #define ICR1 0xA4140010 macro
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/sh/include/asm/ |
| H A D | cpu_sh7720.h | 48 #define ICR1 0xA4140010 macro
|
| /dports/devel/avr-libc/avr-libc-2.0.0/include/avr/ |
| H A D | io2313.h | 99 #define ICR1 _SFR_IO16(0x24) macro
|
| H A D | io43u35x.h | 138 #define ICR1 _SFR_IO16(0x24) macro
|
| H A D | io2333.h | 132 #define ICR1 _SFR_IO16(0x26) macro
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| H A D | io43u32x.h | 127 #define ICR1 _SFR_IO16(0x24) macro
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/sh/include/asm/ |
| H A D | cpu_sh7720.h | 48 #define ICR1 0xA4140010 macro
|
| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/sh/include/asm/ |
| H A D | cpu_sh7720.h | 49 #define ICR1 0xA4140010 macro
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/sh/include/asm/ |
| H A D | cpu_sh7720.h | 48 #define ICR1 0xA4140010 macro
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/sh/include/asm/ |
| H A D | cpu_sh7720.h | 62 #define ICR1 0xA4140010 macro
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/sh/include/asm/ |
| H A D | cpu_sh7720.h | 62 #define ICR1 0xA4140010 macro
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/sh/include/asm/ |
| H A D | cpu_sh7720.h | 62 #define ICR1 0xA4140010 macro
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/sh/include/asm/ |
| H A D | cpu_sh7720.h | 62 #define ICR1 0xA4140010 macro
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/sh/include/asm/ |
| H A D | cpu_sh7720.h | 62 #define ICR1 0xA4140010 macro
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/sh/include/asm/ |
| H A D | cpu_sh7720.h | 62 #define ICR1 0xA4140010 macro
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/sh/include/asm/ |
| H A D | cpu_sh7720.h | 62 #define ICR1 0xA4140010 macro
|
| /dports/emulators/mess/mame-mame0226/src/devices/machine/ |
| H A D | mcf5206e.cpp | 79 return m_ICR[ICR1]; in ICR1_ICR2_ICR3_ICR4_r()
99 m_ICR[ICR1] = data; in ICR1_ICR2_ICR3_ICR4_w()
101 ICR_info(m_ICR[ICR1]); in ICR1_ICR2_ICR3_ICR4_w()
923 m_ICR[ICR1] = 0x04; in init_regs()
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| /dports/emulators/mame/mame-mame0226/src/devices/machine/ |
| H A D | mcf5206e.cpp | 79 return m_ICR[ICR1]; in ICR1_ICR2_ICR3_ICR4_r()
99 m_ICR[ICR1] = data; in ICR1_ICR2_ICR3_ICR4_w()
101 ICR_info(m_ICR[ICR1]); in ICR1_ICR2_ICR3_ICR4_w()
923 m_ICR[ICR1] = 0x04; in init_regs()
|