IDT4_CMD_WRITE (reference) in projects: dports

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Searched refs:IDT4_CMD_WRITE (Results 1 – 4 of 4) sorted by relevance

/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/ethernet/chelsio/cxgb3/
H A D	mc5.c	70 #define IDT4_CMD_WRITE 4 macro 240 t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT4_CMD_WRITE); in init_idt43102() 248 t3_write_reg(adap, A_MC5_DB_DATA_WRITE_CMD, IDT4_CMD_WRITE); in init_idt43102() 259 if (mc5_write(adap, IDT4_GMR_BASE0 + i, IDT4_CMD_WRITE)) in init_idt43102() 263 if (mc5_write(adap, IDT4_GMR_BASE2 + i, IDT4_CMD_WRITE)) in init_idt43102() 267 if (mc5_write(adap, IDT4_GMR_BASE1, IDT4_CMD_WRITE) \|\| in init_idt43102() 268 mc5_write(adap, IDT4_GMR_BASE1 + 1, IDT4_CMD_WRITE) \|\| in init_idt43102() 269 mc5_write(adap, IDT4_GMR_BASE1 + 4, IDT4_CMD_WRITE)) in init_idt43102() 273 if (mc5_write(adap, IDT4_GMR_BASE1 + 5, IDT4_CMD_WRITE)) in init_idt43102() 278 if (mc5_write(adap, IDT4_SCR_ADR0, IDT4_CMD_WRITE)) in init_idt43102() [all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/ethernet/chelsio/cxgb3/
H A D	mc5.c	70 #define IDT4_CMD_WRITE 4 macro 240 t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT4_CMD_WRITE); in init_idt43102() 248 t3_write_reg(adap, A_MC5_DB_DATA_WRITE_CMD, IDT4_CMD_WRITE); in init_idt43102() 259 if (mc5_write(adap, IDT4_GMR_BASE0 + i, IDT4_CMD_WRITE)) in init_idt43102() 263 if (mc5_write(adap, IDT4_GMR_BASE2 + i, IDT4_CMD_WRITE)) in init_idt43102() 267 if (mc5_write(adap, IDT4_GMR_BASE1, IDT4_CMD_WRITE) \|\| in init_idt43102() 268 mc5_write(adap, IDT4_GMR_BASE1 + 1, IDT4_CMD_WRITE) \|\| in init_idt43102() 269 mc5_write(adap, IDT4_GMR_BASE1 + 4, IDT4_CMD_WRITE)) in init_idt43102() 273 if (mc5_write(adap, IDT4_GMR_BASE1 + 5, IDT4_CMD_WRITE)) in init_idt43102() 278 if (mc5_write(adap, IDT4_SCR_ADR0, IDT4_CMD_WRITE)) in init_idt43102() [all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/ethernet/chelsio/cxgb3/
H A D	mc5.c	70 #define IDT4_CMD_WRITE 4 macro 240 t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT4_CMD_WRITE); in init_idt43102() 248 t3_write_reg(adap, A_MC5_DB_DATA_WRITE_CMD, IDT4_CMD_WRITE); in init_idt43102() 259 if (mc5_write(adap, IDT4_GMR_BASE0 + i, IDT4_CMD_WRITE)) in init_idt43102() 263 if (mc5_write(adap, IDT4_GMR_BASE2 + i, IDT4_CMD_WRITE)) in init_idt43102() 267 if (mc5_write(adap, IDT4_GMR_BASE1, IDT4_CMD_WRITE) \|\| in init_idt43102() 268 mc5_write(adap, IDT4_GMR_BASE1 + 1, IDT4_CMD_WRITE) \|\| in init_idt43102() 269 mc5_write(adap, IDT4_GMR_BASE1 + 4, IDT4_CMD_WRITE)) in init_idt43102() 273 if (mc5_write(adap, IDT4_GMR_BASE1 + 5, IDT4_CMD_WRITE)) in init_idt43102() 278 if (mc5_write(adap, IDT4_SCR_ADR0, IDT4_CMD_WRITE)) in init_idt43102() [all …]
/dports/misc/rump/buildrump.sh-b914579/src/sys/dev/pci/cxgb/
H A D	cxgb_mc5.c	76 #define IDT4_CMD_WRITE 4 macro 268 t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT4_CMD_WRITE); in init_idt43102() 276 t3_write_reg(adap, A_MC5_DB_DATA_WRITE_CMD, IDT4_CMD_WRITE); in init_idt43102() 287 if (mc5_write(adap, IDT4_GMR_BASE0 + i, IDT4_CMD_WRITE)) in init_idt43102() 291 if (mc5_write(adap, IDT4_GMR_BASE2 + i, IDT4_CMD_WRITE)) in init_idt43102() 295 if (mc5_write(adap, IDT4_GMR_BASE1, IDT4_CMD_WRITE) \|\| in init_idt43102() 296 mc5_write(adap, IDT4_GMR_BASE1 + 1, IDT4_CMD_WRITE) \|\| in init_idt43102() 297 mc5_write(adap, IDT4_GMR_BASE1 + 4, IDT4_CMD_WRITE)) in init_idt43102() 301 if (mc5_write(adap, IDT4_GMR_BASE1 + 5, IDT4_CMD_WRITE)) in init_idt43102() 306 if (mc5_write(adap, IDT4_SCR_ADR0, IDT4_CMD_WRITE)) in init_idt43102() [all …]